Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations, including initializing a block family associated with the memory device; aggregating temperature values received from one or more temperature sensors of the memory device over time to determine an aggregate temperature; responsive to beginning to program a block residing on the memory device, associating the block with the block family; and in response to the aggregate temperature being greater than or equal to a specified threshold temperature value: performing a soft closure of the block family; initializing an extension timer; continuing to program data to the block; and performing a hard closure of the block family in response to one of the extension timer reaching an extension time value or the block family satisfying a hard closure criteria.

Abstract: A memory sub-system configured to predictively schedule the transfer of data to reduce idle time and the amount and time of data being buffered in the memory sub-system. For example, write commands received from a host system can be queued without buffering the data of the write commands at the same time. When executing a first write command using a media unit, the memory sub-system can predict a duration to a time the media unit becoming available for execution of a second write command. The communication of the data of the second command from the host system to a local buffer memory of the memory sub-system can be postponed and initiated according to the predicted duration. After the execution of the first write command, the second write command can be executed by the media unit without idling to store the data from the local buffer memory.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.

Abstract: Methods, systems, and devices for data stream processing for media management are described. A set of transfer units of a plurality of transfer units associated with a cursor of a garbage collection procedure are selected. The selecting is based on a set of data streams corresponding to the cursor and each transfer unit of the set of transfer units is associated with a same data stream of the set of data streams. A plurality of write commands are issued in connection with the garbage collection procedure for the cursor. Each write command includes an instruction to write a transfer unit of the set of transfer units to a respective destination address of the memory sub-system.

Abstract: Apparatus and method for managing metadata in a data storage device, such as a solid-state drive (SSD). In some embodiments, a non-volatile memory (NVM) includes a population of semiconductor memory dies. The dies are connected a number of parallel channels such that less than all of the semiconductor dies are connected to each channel. A controller circuit apportions the semiconductor memory dies into a plurality of die sets, with each die set configured to store user data blocks associated with a different user. A separate set of map data is generated to describe user data blocks stored to each die set. The controller circuit stores the respective sets of map data in the associated die sets so that no die set stores map data associated with a different die set. The die sets may be arranged in accordance with the NVMe (Non-Volatile Memory Express) specification.

Abstract: Systems and methods are disclosed for data storage performance scaling based on external energy. In certain embodiments, a system may comprise a data storage device having an interface to communicate with an external device, a nonvolatile memory, and a circuit. The circuit may be configured to receive an indication via the interface of power resources available to the data storage device from the external device in case of a power loss event, adjust a performance metric of the data storage device to apply when accessing the nonvolatile memory during normal power availability based on the indication, and perform operations during normal power availability based on the performance metric.

Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations, including initializing a block family associated with the memory device; aggregating temperature values received from one or more temperature sensors of the memory device over time to determine an aggregate temperature; responsive to beginning to program a block residing on the memory device, associating the block with the block family; and in response to the aggregate temperature being greater than or equal to a specified threshold temperature value: performing a soft closure of the block family; initializing an extension timer; continuing to program data to the block; and performing a hard closure of the block family in response to one of the extension timer reaching an extension time value or the block family satisfying a hard closure criteria.

Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations, including initializing a block family associated with the memory device and initializing a timer associated with the block family. Responsive to beginning to program a block residing on the memory device, the processing device associates the block with the block family. In response to the timer reaching a soft closure value, the processing device performs a soft closure of the block family; continues to program data to the block; and performs a hard closure of the block family in response to one of the timer reaching a hard closure value or the block family satisfying a hard closure criteria.

Abstract: Methods, systems, and devices for data stream processing for media management are described. A set of transfer units of a plurality of transfer units associated with a cursor of a garbage collection procedure are selected. The selecting is based on a set of data streams corresponding to the cursor and each transfer unit of the set of transfer units is associated with a same data stream of the set of data streams. A plurality of write commands are issued in connection with the garbage collection procedure for the cursor. Each write command includes an instruction to write a transfer unit of the set of transfer units to a respective destination address of the memory sub-system.

Abstract: A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

Abstract: A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations, including initializing a block family associated with the memory device and initializing a timer associated with the block family. Responsive to beginning to program a block residing on the memory device, the processing device associates the block with the block family. In response to the timer reaching a soft closure value, the processing device performs a soft closure of the block family; continues to program data to the block; and performs a hard closure of the block family in response to one of the timer reaching a hard closure value or the block family satisfying a hard closure criteria.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.

Abstract: A semiconductor data storage memory can receive data access commands into a queue in a first time sequence that correspond with the transfer of data between a host and portions of the memory. The memory may be divided into separate portions that each have a different owner and the access commands may be issued to each of the respective separate portions. The access commands can subsequently be executed in a different, second time sequence responsive to estimated completion times for each of the access commands based on measured completion times for previously serviced, similar commands to maintain a nominally consistent quality of service level for each of the respective owners.

Abstract: Apparatus and method for storing data in a non-volatile memory (NVM), such as a flash memory in a solid-state drive (SSD). In some embodiments, a distributed storage space of the NVM is defined to extend across a plural number of regions of the NVM. A non-standard parity data set is provided having a plural number of data elements greater than or equal to the plural number of regions in the storage space. The data set is written by storing a first portion of the data elements and a first parity value to the plural number of regions and a remaining portion of the data elements and a second parity value to a subset of the plural number of regions. The regions can comprise semiconductor dies in a flash memory, and the distributed storage space can be a garbage collection unit formed using one erasure block from each flash die.

Abstract: Methods, systems, and devices for data stream processing for media management are described. A set of transfer units of a plurality of transfer units associated with a cursor of a garbage collection procedure are selected. The selecting is based on a set of data streams corresponding to the cursor and each transfer unit of the set of transfer units is associated with a same data stream of the set of data streams. A plurality of write commands are issued in connection with the garbage collection procedure for the cursor. Each write command includes an instruction to write a transfer unit of the set of transfer units to a respective destination address of the memory sub-system.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.

Abstract: Apparatus and method for managing entropy in a cryptographic processing system, such as but not limited to a solid-state drive (SSD). In some embodiments, a processing device is operated to transfer data between a host device and a non-volatile memory (NVM). In response to the detection of a power down event associated with the processing device, entropy associated with the power down event is collected and stored in a memory. Upon a subsequent reinitialization of the processing device, the entropy is conditioned and used as an input to a cryptographic function to subsequently transfer data between the host device and the NVM. In some embodiments, the entropy is obtained from the state of a hardware timer that provides a monotonically increasing count for timing control. In other embodiments, the entropy is obtained from a RAID buffer used to store data to a die set of the NVM.

Abstract: Apparatus and method for managing metadata in a data storage device, such as a solid-state drive (SSD). In some embodiments, a non-volatile memory (NVM) includes a population of semiconductor memory dies. The dies are connected a number of parallel channels such that less than all of the semiconductor dies are connected to each channel. A controller circuit apportions the semiconductor memory dies into a plurality of die sets, with each die set configured to store user data blocks associated with a different user. The controller circuit subsequently rearranges the dies into a different arrangement of die sets so that at least one die is migrated from a first dies set to a second die set. A map manager circuit is configured to establish an array of pointers in a memory to identify contiguous portions of map metadtata that describe user data stored in the at least one migrated die.