Abstract: A storage system in one embodiment comprises at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory. The input-output controller generates a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts. If an address of a given one of the write commands falls within a specified interrupt group window, the write command is copied to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device. The directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor.

Abstract: A storage system in one embodiment comprises at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory. The input-output controller generates a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts. If an address of a given one of the write commands falls within a specified interrupt group window, the write command is copied to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device. The directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor.

Abstract: A storage system in one embodiment comprises at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory. The input-output controller generates a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts. If an address of a given one of the write commands falls within a specified interrupt group window, the write command is copied to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device. The directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor.

Abstract: A method includes obtaining instructions at a mobile device comprising directions from a current location of the mobile device to a target location in a facility over a path identified by two or more waypoint devices distributed in the facility, receiving signaling over at least one wireless network from a selected one of the waypoint devices in the path, utilizing a radio frequency signal strength of the received signaling to estimate proximity between the mobile device and the selected waypoint device, presenting an indication of proximity to the first waypoint device via the mobile device based at least in part on the estimated proximity, determining whether the estimated proximity between the mobile device and the selected waypoint device is below a proximity threshold, and selecting another one of the waypoint devices in the path responsive to determining that the estimated proximity is below the proximity threshold.

Abstract: In a highly available storage system, an enclosure includes first and second power supplies, and first and second controller boards. Each of the first and second controller boards includes first and second serial bus controllers. First and second serial buses are coupled to both of the first and second serial bus controllers on each of the first and second controller boards. The first serial bus is coupled to the first power supply, while the second serial bus coupled to the second power supply. The first and second serial buses are used for exchanging enclosure management and environmental information between the first and second power supplies and the first and second controller boards. The first and second serial buses are coupled to isolation switches so that redundant modules can operate if a serial bus controller fails.

Abstract: Communications paths are managed. An error is detected on a first storage processor. It is determined that the error resulted from a peer-to-peer communication from a second storage processor. The error on the first storage processor is handled by taking action short of causing the first storage processor to reset.

Abstract: System availability is managed. It is determined that a data communications link has been established and that the data communications link is less than fully functional. Communication is performed across the data communications link to a device to configure the device for the data communications link. The device is caused to re-establish the data communication link based on the results of the configuring.

Abstract: System components are managed. Based on a first communication path to a component, first identification information for the component is determined. Based on a second communication path to the component, second identification information for the component is determined. Based on the first identification information and the second identification information, an identity for the component is determined. Based on the identity, a set of tests is performed on the component. Based on the failure rate of the set of tests, it is concluded that another component on the first communication path is faulty.

Abstract: Disclosed is a system including a circuit board and several pluggable modules coupled to the circuit board. The several pluggable modules are insertable through side-by-side slots in an enclosure in which the circuit board resides. A first pluggable module is coupled to the circuit board via a first connector, while a second pluggable module is coupled to the circuit board via a second connector such that the second pluggable module is laterally offset from the first pluggable module. The first and second connectors are right angle connectors, and the second right angle connector is inverted relative to the first right angle connector. The first and second pluggable modules are I/O modules for transporting high speed differential signals, and wherein the first pluggable module includes several XFP connectors, and wherein the second pluggable module includes several SFP connectors. The second pluggable module includes several SFP connectors arranged on both sides of the pluggable module.

Abstract: A system having expansion slots is capable of multiple configurations. In a first configuration, a first blade is coupled to a first module via a first expansion slot and a second blade is coupled to a second module via a second expansion slot. The first and second modules may be I/O modules such as PCI Express modules. In a second configuration the first and second blades are both coupled to a third module via the first and second expansion slots. The third module may be a shared resource such as a cache card.

Abstract: Described is an enclosure that is configurable to perform either in-band or out-of-band enclosure management. The enclosure includes a midplane, a processor module, and a management module. The processor module has program code for collecting management information from other components in the enclosure. If the enclosure is configured for in-band enclosure management, the processor module executes the program code to collect the management information. If the enclosure is configured for out-of-band enclosure management, the management module is configured to execute program code for collecting the management information instead of the processor module.

Abstract: A data storage system includes a first storage processor including a first memory device; a second storage processor including a second memory device; and a third memory device coupled to the first storage processor and the second storage processor. The first and second storage processors are interconnected to enable mirroring of data between the first memory device and the second memory device. During a first mode of operation, data processed by the first storage processor and the second storage processor is mirrored between the first memory device and the second memory device and, during a second mode of operation, data processed by the first storage processor is mirrored from the first memory device to the third memory device.

Abstract: Disclosed is a system including a circuit board and several pluggable modules coupled to the circuit board. The several pluggable modules are insertable through side-by-side slots in an enclosure in which the circuit board resides. A first pluggable module is coupled to the circuit board via a first connector, while a second pluggable module is coupled to the circuit board via a second connector such that the second pluggable module is laterally offset from the first pluggable module. The first and second connectors are right angle connectors, and the second right angle connector is inverted relative to the first right angle connector. The first and second pluggable modules are I/O modules for transporting high speed differential signals, and wherein the first pluggable module includes several XFP connectors, and wherein the second pluggable module includes several SFP connectors. The second pluggable module includes several SFP connectors arranged on both sides of the pluggable module.