Abstract: Methods and apparatus for preprocessing commands by a data transfer device. A prefetch processor creates a list of contiguous pointers in a local memory coupled to a controller CPU, based on pointers stored by a host processing system coupled to the data transfer device. When the controller CPU is ready to execute a command, it uses the pointer list in the local memory to determine where to transfer data associated with the command.

Abstract: A method and apparatus for reducing the time for rebuilding a memory mapping table in a host computer. A memory mapping table is maintained by a host computer in dynamic memory and duplicated in a data storage device, for example, a solid state drive (SSD). If power is lost, a rebuild engine inside the data storage device separate and apart from a controller CPU rebuilds the memory mapping table in the dynamic memory based on a copy of the memory mapping table maintained by the data storage device.

Abstract: Methods and apparatus are described to dynamically adjust internal resources and arbitration schemes of a block I/O device that allows for efficient bandwidth utilization and increased IO performance of the block I/O device. Commands from a plurality of hosts are monitored and measured under various workloads, and the block I/O device dynamically adjusts internal resources and arbitration schemes based on the received commands.

Abstract: A system, method and apparatus for encrypting data. A host processor and host memory are coupled to a block I/O device. The host processor issues encryption and decryption commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device performs encryption on data specified in the encryption command, thus relieving the host processor of performing the encryption and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for encoding and decoding data. A host processor and host memory are coupled to a block I/O device. The host processor issues encode and decode commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device encodes the data specified in the encode command, thus relieving the host processor of performing the encoding/decoding and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for compressing and decompressing data. A host processor and host memory are coupled to a block I/O device. The host processor issues compress and decompress commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device compresses/decompresses the data specified in the compress/decompress command, thus relieving the host processor of performing the compression/decompression and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for encrypting data. A host processor and host memory are coupled to a block I/O device. The host processor issues encryption and decryption commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device performs encryption on data specified in the encryption command, thus relieving the host processor of performing the encryption and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for encoding and decoding data. A host processor and host memory are coupled to a block I/O device. The host processor issues encode and decode commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device encodes the data specified in the encode command, thus relieving the host processor of performing the encoding/decoding and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for encrypting data. A host processor and host memory are coupled to a block I/O device. The host processor issues encryption and decryption commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device performs encryption on data specified in the encryption command, thus relieving the host processor of performing the encryption and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for compressing and decompressing data. A host processor and host memory are coupled to a block I/O device. The host processor issues compress and decompress commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device compresses/decompresses the data specified in the compress/decompress command, thus relieving the host processor of performing the compression/decompression and freeing the host processor for other tasks.

Abstract: Described embodiments provide for switching from a low-power mode of a device such as, for example, a SAS or SATA receiver, to an active mode. The device enters the low-power mode by shutting down i) logic devices of a physical layer of the device and ii) a decoding circuit of the device. Activity at an input of a receiver of the device is detected while in low-power mode, and the device switches, in response to the detected activity, from the low-power mode to the active mode by powering up i) the logic devices of the physical layer and ii) the decoding circuit when activity is detected, thereby responding to the detected activity as if it is a predetermined command.

Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.

Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.