Abstract: A method and system are provided to detect and correct errors in the Interlaken block code overhead bits. Specifically, a method is provided for determining the original transmitted information with a very high probability of correct interpretation. These approaches can also characterized by their minimal complexity. Further, such a method can operate on the received information in a manner that does not require consideration of special cases. Also, the method does not require the source to send any extra information or alter its current behavior in any way. Thus, the approaches described herein are compatible with all existing Interlaken sources and can provide immediate benefits.

Abstract: A method of communicating count value information in an Optical Transport Network (OTN) signal frame. The method comprises determining a count value indicating a number of payload bytes to be sent in a next OTN signal frame; determining that a change in the count value (?) with respect to a current count value is within a predetermined range; selecting an inversion pattern indicating the change in the count value; determining a cyclic redundancy check (CRC) code associated with the inversion pattern; and, inserting the inversion pattern and the CRC code in a Generic Mapping Procedure (GMP) overhead of the OTN signal frame.

Abstract: Asynchronous/plesiochronous digital hierarchy (PDH) signals, such as DS1 and E1, are transported using virtual concatenation. The packetized data signals are frame encapsulated and subsequently inverse multiplexed into a plurality of PDH frames. An overhead packet is inserted in the transmitted frames to enable the receiver to determine the status of the frames and extract the differential delay experienced by various frames as they are routed through virtually concatenated channels. The extracted delays enables the receiver to realign the various frames of the PDH signal to reconstitute the originally transmitted signals that travel through different paths of the transport network linking the source and sink of the virtually concatenated channel.

Abstract: Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors even when those errors are not confined to a single block. Disclosed techniques permit a reduction in the amount of forward error correction used. For example, in general, to correct t errors, a linear cyclic error correction code requires a Hamming distance of at least 1+(2t)[wt(s(x))]. Embodiments of the invention allow correcting the multiplied errors with a Hamming distance of only 1+(t)(1+wt(s(x))) over the block size n, wherein wt(s(x)) is the weight of the scrambler polynomial s(x).

Abstract: Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors even when those errors are not confined to a single block. Disclosed techniques permit a reduction in the amount of forward error correction used. For example, in general, to correct t errors, a linear cyclic error correction code requires a Hamming distance of at least 1+(2t)[wt(s(x))]. Embodiments of the invention allow correcting the multiplied errors with a Hamming distance of only 1+(t)(1+wt(s(x))) over the block size n, wherein wt(s(x)) is the weight of the scrambler polynomial s(x).

Abstract: A system and method are provided to detect an extended error burst in a data interface. An original error burst has a given length prior to or during transmission. Data transmission processing can extend the original error burst beyond its original length to become an extended error burst with an effective length greater than the original error burst length. Such data transmission processing can include: de-interleaving data on a multi-lane data interface; feedback from a Decision Feedback Equalizer (DFE) receiver; and/or block line decoding, such as 8B/10B block line code decoding. An extended error burst detector can include a suitable error detecting code, such as an r-bit cyclic redundancy check (CRC) code developed in relation to known extended error burst patterns, to detect all extended error bursts based on an up to r-bit original error burst. The detector can also detect error bursts that are not extended beyond the original error burst length.

Abstract: Signature circuits are used during testing of an integrated circuit. Test vectors are applied as inputs to a circuit under test. A signature circuit stores a “signature” for the circuit under test based on a combination of signals from the circuit under test in response to test vectors and a previous stored state of the signature register. The value contained in the signature register at the end of the test is the signature. A fault-free circuit generates a particular signature for the applied test vectors. Faults can be determined by detecting variances from the expected signature. In one embodiment, the signature circuit uses a combination of two error detection codes.

Abstract: The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. At the end of a CRC error detection division operation, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.

Abstract: The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. At the end of a CRC error detection division operation, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.

Abstract: A method and/or system and/or apparatus for mapping a protocol including data and a limited number of control codes to an efficient encoding protocol for carrying on various other networks, particularly those with parallel processing. In specific embodiments, the invention decodes 8b/10b type data to 8b data, and then maps the data into transparent GFP frames or blocks and can further map the frames into superblocks of frames and in further embodiments add padding characters on the fly to constructed blocks to reduce buffering needed and to reduce variable delay created during frame construction.

Abstract: The present invention preferably places a hardware circuit between the SCU's ARCNET transceiver and the backplane bus rather than a parallel snooper circuit. This circuit builds the map based on the tokens it observes. When the circuit detects the token for the SCU, it blocks the token transmission to the SCU's ARCNET transceiver. It then sends a minimum length “ping” message to each unit that was present on the bus during the last token rotation, but is not present during the token rotation that just ended. Since units that have lost their token can still respond to a Free Buffer Enquiry message, the circuit can use it as a ping to verify whether the missing unit(s) are actually missing or have just lost their token due to noise. After verification, the token is forwarded to the SCU's ARCNET transceiver.

Abstract: A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween. The interface having: a common bus of predetermined bit width for interfacing the HSU unit with each of the LSU units to enable transmission of signals from each of the LSUs to the HSU, and reception of the signals from the HSU to each of the LSUs; a first partition bus of the predetermined bit width for interfacing the HSU to a predetermined number of the LSUs, the first partition bus being partitioned into a first bus for interfacing the HSU to a first subset of the LSUs and a second bus for interfacing the HSU to a second subset of the LSUs; and a second partition bus of the predetermined bit width for interfacing the HSU to a predetermined number of the LSU units.

Abstract: A SONET network interface for interconnecting a high speed unit (HSU) with low speed interface units (LSUs) to enable transmission of signals therebetween. The interface including: a bus for interfacing the HSU with each of the LSU units to enable transmission of signals from each of LSUs to the HSU, and reception of the signals from the HSU to each of the LSUs; and a backplane connected to the bus and having at least two time slots for performing full time slot interchange between the at least two LSUs, wherein any of the at least two LSUs can read received data directly from one of the at least two time slots and can place its transmit data into any other of the at least two time slots for communication with another of the at least two LSUs without exchanging the received and/or transmit data with the at least one HSU.

Abstract: The present invention provides a circuit for detecting and correcting errors in a bit stream. The circuit consist of a plurality of circuit elements, an least operation circuit means, and at least two logic gates. The logic gates receive inputs from the plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. The operation circuit elements perform bitwise operations on the contents of at least two of the circuit elements. The bitwise operations are dictated by a CRC polynomial and are used to perform the CRC error detection division operation. At the end of the division process for the data to be checked, each circuit element corresponds to a bit in a bit error pattern, the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns.

Abstract: A SONET network interface for interconnecting a high speed unit (HSU) with low speed interface units (LSUs) is provided for enabling transmission of signals therebetween. The interface includes: a bus for interfacing the HSU with each of the LSUs to enable transmission of signals from each of the LSUs to the HSU, and reception of the signals from the HSU to each of the LSUs, wherein the HSU, LSUs, and the bus are contained in a primary shelf. The network interface also has secondary shelves, each containing secondary LSUs and an intershelf ring interconnection (IRI) bus connecting the primary shelf and each of the secondary shelves in series for exchanging data between the HSU of the primary shelf and each of the secondary shelves.

Abstract: The present invention preferably places a hardware circuit between the SCU's ARCNET transceiver and the backplane bus rather than a parallel snooper circuit. This circuit builds the map based on the tokens it observes. When the circuit detects the token for the SCU, it blocks the token transmission to the SCU's ARCNET transceiver. It then sends a minimum length “ping” message to each unit that was present on the bus during the last token rotation, but is not present during the token rotation that just ended. Since units that have lost their token can still respond to a Free Buffer Enquiry message, the circuit can use it as a ping to verify whether the missing unit(s) are actually missing or have just lost their token due to noise. After verification, the token is forwarded to the SCU's ARCNET transceiver.

Abstract: A system for providing 1:n protection for common processing units in a star bus architecture multiplexer or switching system and providing one redundant protection common processing unit to protect up to n working common processing units has a pair of first and second common processing slots (C) for common processing units, a plurality of tributary interface slots (T) for tributary interface units, and at least one universal slot (U) for accommodating either an additional common processing unit or a tributary interface unit. If the working on-line common processing unit of the dedicated pair fails, the protection common processing unit takes over for the failed common processing unit. If one of the additional common processing units fails, the dedicated protection common processing unit takes over, thereby providing 1:n protection regardless of where each common processing unit is located.