Abstract: Embodiments described herein provide a mission-critical artificial intelligence (AI) processor (MAIP), which includes an instruction buffer, processing circuitry, a data buffer, command circuitry, and communication circuitry. During operation, the instruction buffer stores a first hardware instruction and a second hardware instruction. The processing circuitry executes the first hardware instruction, which computes an intermediate stage of an AI model. The data buffer stores data generated from executing the first hardware instruction. The command circuitry determines that the second hardware instruction is a hardware-initiated store instruction for transferring the data from the data buffer. Based on the hardware-initiated store instruction, the communication circuitry transfers the data from the data buffer to a memory device of a computing system, which includes the mission-critical processor, via a communication interface.

Abstract: A scalar element computing device for computing a selected activation function selected from two or more different activation functions is disclosed. The scalar element computing device comprises N processing elements, N command memories and an operator pool. The N processing elements are arranged into a pipeline to cause the outputs of each non-last-stage processing element coupled to the inputs of one next-stage processing element. The N command memories are coupled to the N processing elements individually. The operator pool is coupled to the N processing elements, where the operator pool comprises a set of operators for implementing any activation function in an activation function group. The N processing elements are configured according to command information stored in the N command memories to calculate a target activation function selected from the activation function group by using one or more operators in the set of operations.

Abstract: Embodiments described herein provide a mission-critical artificial intelligence (AI) processor (MAIP), which includes an instruction buffer, processing circuitry, a data buffer, command circuitry, and communication circuitry. During operation, the instruction buffer stores a first hardware instruction and a second hardware instruction. The processing circuitry executes the first hardware instruction, which computes an intermediate stage of an AI model. The data buffer stores data generated from executing the first hardware instruction. The command circuitry determines that the second hardware instruction is a hardware-initiated store instruction for transferring the data from the data buffer. Based on the hardware-initiated store instruction, the communication circuitry transfers the data from the data buffer to a memory device of a computing system, which includes the mission-critical processor, via a communication interface.