Patents by Inventor Steven Shrader
Steven Shrader has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9448883Abstract: A system and method are provided for efficient allocation of data in a memory array having regions of varying storage reliability. Storage locations for bands of data are selectively allocated in a manner which evenly distributes the probability of error in the data when stored in the memory array in spite of the varying storage reliability. A distribution controller is provided to effect such distribution of data to maintain a collective error rate of each data band within a preselected or predetermined range. The system and method also generally provide for storing at least a first and a second data band in different corresponding sets of storage channels. The system and method also generally provide for at least one of the data bands being stored in regions of differing reliability across the set of storage channels therefor.Type: GrantFiled: December 4, 2012Date of Patent: September 20, 2016Assignee: Cadence Design Systems, Inc.Inventor: Steven Shrader
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Publication number: 20160006808Abstract: An electronic system includes: a network; a memory device, coupled to the network; a host processor, coupled to the network and the memory device, providing a transaction protocol including cut through.Type: ApplicationFiled: February 25, 2015Publication date: January 7, 2016Inventor: Steven Shrader
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Publication number: 20150363312Abstract: An electronic system includes: a second memory module; a first memory module coupled to the second memory module; and a multicast controller for managing a cache on the first memory module for the second memory module.Type: ApplicationFiled: December 8, 2014Publication date: December 17, 2015Inventors: Hongzhong Zheng, Krishna Malladi, Steven Shrader
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Patent number: 8627169Abstract: An invention is provided for dynamically configurable error correction. The invention includes receiving a check code configuration signal, which indicates a particular level of error detection. A check code generator is configured to generate check codes based on the particular level of error detection indicated by the check code configuration signal. In addition, an error locator configuration signal is received that indicates a particular level of error addressing, and an error locator is configured to produce addresses of errors in a set of data based on the particular level of error addressing indicated by the error locator configuration signal.Type: GrantFiled: June 20, 2008Date of Patent: January 7, 2014Assignee: Cadence Design Systems, Inc.Inventor: Steven Shrader
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Patent number: 8201058Abstract: An invention is provided for parallel ECC error location in a memory. The invention includes partitioning a set of field elements into w partitions. Then, for each of the w partitions of field elements, i) providing a set of r different field elements of the partition to r parallel search element. Next, in operation ii), each parallel search element computes a sum that is based on a set of coefficients of an error locator polynomial and the field element provided to the particular parallel search element. The set of field elements is advanced r field elements in GF(2m), and operations i) through iii) are repeated using the next r different field elements of the partition.Type: GrantFiled: July 9, 2008Date of Patent: June 12, 2012Assignee: Cadence Design Systems, Inc.Inventors: Steven Shrader, Anujan Varma, Mohit Mittal
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Patent number: 8099567Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.Type: GrantFiled: July 31, 2009Date of Patent: January 17, 2012Assignee: Cadence Design Systems, Inc.Inventors: Steven Shrader, Michael McKeon
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Publication number: 20100011247Abstract: An invention is provided for parallel ECC error location in a memory. The invention includes partitioning a set of field elements into w partitions. Then, for each of the w partitions of field elements, i) providing a set of r different field elements of the partition to r parallel search element. Next, in operation ii), each parallel search element computes a sum that is based on a set of coefficients of an error locator polynomial and the field element provided to the particular parallel search element. The set of field elements is advanced r field elements in GF(2m), and operations i) through iii) are repeated using the next r different field elements of the partition.Type: ApplicationFiled: July 9, 2008Publication date: January 14, 2010Applicant: Denali Software, Inc.Inventors: Steven Shrader, Anujan Varma, Mohit Mittal
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Publication number: 20090319864Abstract: An invention is provided for dynamically configurable error correction. The invention includes receiving a check code configuration signal, which indicates a particular level of error detection. A check code generator is configured to generate check codes based on the particular level of error detection indicated by the check code configuration signal. In addition, an error locator configuration signal is received that indicates a particular level of error addressing, and an error locator is configured to produce addresses of errors in a set of data based on the particular level of error addressing indicated by the error locator configuration signal.Type: ApplicationFiled: June 20, 2008Publication date: December 24, 2009Applicant: DENALI SOFTWARE, INC.Inventor: Steven Shrader
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Publication number: 20090292886Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.Type: ApplicationFiled: July 31, 2009Publication date: November 26, 2009Inventors: Steven Shrader, Michael McKeon
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Patent number: 7574573Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.Type: GrantFiled: October 9, 2007Date of Patent: August 11, 2009Assignee: Denali Software, Inc.Inventors: Steven Shrader, Michael McKeon
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Publication number: 20080091890Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.Type: ApplicationFiled: October 9, 2007Publication date: April 17, 2008Inventors: Steven Shrader, Michael McKeon
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Patent number: 7299324Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.Type: GrantFiled: November 5, 2003Date of Patent: November 20, 2007Assignee: Denali Software, Inc.Inventors: Steven Shrader, Michael McKeon
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Patent number: 7100002Abstract: A port independent data transaction interface for multi-port devices is provided. The port independent data transaction interface includes a command channel that receives command data and a source id. The source id indicates a source device that transmitted the command data. In addition, a data-in channel is included that receives write data and a write source id. Similar to the source id, the write source id indicates a source device that transmitted the write data. The port independent data transaction interface further includes a data-out channel that provides read data and a read id. The read id indicates a source device that transmitted a read command corresponding to the read data. The port independent data transaction interface utilizes the source id to associate command data with corresponding write data and read data.Type: GrantFiled: September 16, 2003Date of Patent: August 29, 2006Assignee: Denali Software, Inc.Inventors: Steven Shrader, Samitinjoy Pal, Anne Espinoza, Michael McKeon
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Patent number: 7062625Abstract: An interface for sending write data, write control signals and write data between a memory controller and a double data rate (DDR) memory with the appropriate timing relationships so that the write data can be reliably written in the DDR memory. Also, an interface for reliably capturing read data received from the DDR memory during a read operation.Type: GrantFiled: July 31, 2002Date of Patent: June 13, 2006Assignee: Denali Software, Inc.Inventors: Steven Shrader, Art Gmurowski, Samitinjoy Pal, Michael McKeon
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Patent number: 7054968Abstract: A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data from a port to be selected for processing. A state machine is in communication with the arbitration module. The state machine is configured to generate a signal to the arbitration module that is configured to select the data associated with the port based upon the latency factor and the bandwidth factor. Task status and completion circuitry configured to calculate the bandwidth factor based upon previous data selected from the port is included in the initiator block. The task status and completion circuitry is further configured to transmit the calculated bandwidth factor to the state machine. A method for arbitrating across multiple ports is also provided.Type: GrantFiled: September 16, 2003Date of Patent: May 30, 2006Assignee: Denali Software, Inc.Inventors: Steven Shrader, Wendy Bishop, Ashwin Matta
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Publication number: 20050097265Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.Type: ApplicationFiled: November 5, 2003Publication date: May 5, 2005Applicant: Denali Software, Inc.Inventors: Steven Shrader, Michael McKeon
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Publication number: 20050060456Abstract: A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data from a port to be selected for processing. A state machine is in communication with the arbitration module. The state machine is configured to generate a signal to the arbitration module that is configured to select the data associated with the port based upon the latency factor and the bandwidth factor. Task status and completion circuitry configured to calculate the bandwidth factor based upon previous data selected from the port is included in the initiator block. The task status and completion circuitry is further configured to transmit the calculated bandwidth factor to the state machine. A method for arbitrating across multiple ports is also provided.Type: ApplicationFiled: September 16, 2003Publication date: March 17, 2005Inventors: Steven Shrader, Wendy Bishop, Ashwin Matta
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Publication number: 20050060501Abstract: A port independent data transaction interface for multi-port devices is provided. The port independent data transaction interface includes a command channel that receives command data and a source id. The source id indicates a source device that transmitted the command data. In addition, a data-in channel is included that receives write data and a write source id. Similar to the source id, the write source id indicates a source device that transmitted the write data. The port independent data transaction interface further includes a data-out channel that provides read data and a read id. The read id indicates a source device that transmitted a read command corresponding to the read data. The port independent data transaction interface utilizes the source id to associate command data with corresponding write data and read data.Type: ApplicationFiled: September 16, 2003Publication date: March 17, 2005Applicant: Denali Software, Inc.Inventors: Steven Shrader, Samitinjoy Pal, Anne Espinoza, Michael McKeon
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Patent number: 6665230Abstract: Circuitry for programming the amount of delay applied to an input signal, the circuitry performing the method of determining the number of delay elements required to capture a clock cycle, receiving a programmable delay value and calculating the number of delay elements required to delay a clock signal by the received delay value and delaying the clock signal by the number of delay elements required to delay the clock signal by the programmable delay value.Type: GrantFiled: July 31, 2002Date of Patent: December 16, 2003Assignee: Denali Software, Inc.Inventors: Steven Shrader, Art Gmurowski, Samitinjoy Pal, Michael McKeon