Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.

Abstract: A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

Abstract: A receiver may be adapted to prevent overflow or underflow of its data storage by generating a transmit rate value as a feedback to the sender. Speed adjustments are performed periodically with a fixed time period denoted by Dt. Transmission rates are explicitly 0, Max/2, and Max. The receiver queue is itself drained at a rate R that at any time satisfies 0<=R<=Max. The level of occupancy of the receiver storage queue is denoted by Q. The maximum capacity of the receiving queue is designated Qmax, so at any time, 0<=Q<=Qmax. Two thresholds T1 and T2 (with 0<T1<T2<Qmax) of levels of the receiver queue value Q are determined. A transmit rate is then determined by the level of the receiver queue Q compared to the thresholds. The transmit rate feedback value achieves the desired goal of avoiding overflow and, once the value of Q has been positive at least once, avoiding underflow.

Abstract: A method for dynamically adjusting the flow rate of a plurality of logical pipes that share a common output queue. In accordance with the method of the present invention, a minimum flow rate and a maximum flow rate are set for each of the pipes. Next a determination is made of whether or not excess queue bandwidth exists in accordance with the output flow rate of the shared queue. The determination of whether or not excess bandwidth exists comprises comparing the output flow rate of the shared queue with a pre-determined threshold queue output value. An instantaneous excess bandwidth signal has a value of 1 if there is excess bandwidth and is otherwise 0 if there is no excess bandwidth. In an alternate embodiment, the instantaneous excess bandwidth signal for a particular pipe is logically ANDed with one or more additional excess bandwidth signals to form a composite instantaneous excess bandwidth signal.

Abstract: A data processing system and method in a computer network are disclosed for improving performance of a link aggregation system included in the network. Parameters are established which are utilized to determine performance criteria of the link aggregation system. A performance of the link aggregation system is determined by determining the performance criteria. The performance of the link aggregation system changes in response to a flow traffic burden on the link aggregation system changing. The link aggregation system dynamically modifies the parameters in response to the changing performance of the link aggregation system. The link aggregation system is self-tuning and capable of automatically adjusting to a changing flow traffic burden on the link aggregation system.

Abstract: The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In one aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full ‘read’ and 4 banks of full ‘write’ by the network processor for every repetition of the DRAM time clock. A scheme for randomized ‘read’ and ‘write’ access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variable frame sizes.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.

Abstract: A method and system for systematically accessing and monitoring operating parameter signals within an IC device. A probe configuration logic selects a subset of signals from among a set of available signals within a physical or logical subdivision of the IC device. Signal access logic selectively provides physical or logical access from the selected subset of signals within the physical or logical subdivision of the IC device to a probe sensor, such that IC device operations may be flexibly and comprehensively monitored. A local mode selector provides remote access to the selected subset of signals at an input/output (I/O) data interface. Data packaging logic in communication with the probe sensor permits port mirroring of the I/O data interface.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Abstract: A system and method of moving information units from an output flow control toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to service based on a weighted fair queue where position in the queue is adjusted after each service based on a weight factor and the length of frame, a process which provides a method for and system of interaction between different calendar types is used to provide minimum bandwidth, best effort bandwidth, weighted fair queuing service, best effort peak bandwidth, and maximum burst size specifications. The present invention permits different combinations of service that can be used to create different QoS specifications.

Abstract: An apparatus for use in token ring switches for selectively setting the A/C bits in token ring frames. The apparatus includes a database with addresses of stations on the ring connected to the port. The apparatus compares the destination addresses of frames received from the ring with the addresses in the database and sets the A/C bits only if a match does not occur. By setting the A/C bits selectively, by the port, errors that would otherwise occur, either by setting the A/C bits on all frames or not setting the bits on all frames, are obviated.

Abstract: Methods, systems and computer program products are provided which control message storms in a network by classifying multiple destination messages into a plurality of broadcast message classes based upon characteristics of the broadcast messages. The number of multiple destination messages for each class of broadcast messages of the plurality of classes of broadcast messages are then counted so as to provide a plurality of broadcast message class counts. Multiple destination messages of a class of broadcast messages are then selectively transmitted based upon the broadcast message class count for the class of broadcast messages.

Abstract: Methods for identifying compounds that can be used for treatment of neurodegenerative diseases, for monitoring the progression of these diseases, and for monitoring therapeutic intervention of these diseases are provided. These methods are effected by determining the relative amount of .alpha.-sAPP and the ratio of .alpha.-sAPP to total sAPP in body fluids, tissues or in cell culture.

Abstract: A device for interconnecting Local Area Networks (LANs) includes ports for attaching LAN segments and port modules for connecting the ports to a switch fabric. Each of the port modules include a mechanism which searches the Routing Information (RI) field of a Received frame to detect at least two Triplets (a minimum configuration for a LAN segment) indicating a Source path from an originator user and a Destination path to a destination user. The Triplet (single or in combination) is used to access a database (tables) which identifies the Port of Exit (POE) through which the frame is to be routed.

Abstract: Methods of use of compounds for the treatment of disorders characterized by the cerebral deposition of amyloid are provided. Among the compounds provided for use in the methods are those of the formula: ##STR1## in which R.sub.1 is preferably 2-methylpropenyl, 2-butenyl, cyclohexyl or cyclohexylmethyl; R.sub.2, R.sub.4, and R.sub.8 are each preferably independently methyl or ethyl; R.sub.3 is preferably iso-butyl or phenyl; Q is preferably --C(O)--; R.sub.B is preferably iso-butyl; R.sub.A is --(T).sub.m --(D).sub.m --R.sub.1, in which T is preferably oxygen or NH, m is 0 or 1, and D is preferably C.sub.1-4 alkyl or C.sub.2-4 alkenyl; and X is preferably an aldehyde, .alpha.-ketoester or .alpha.-ketoamide.

Abstract: A design control system suitable for use in connection with the design of integrated circuits and other elements of manufacture having many parts which need to be developed in a concurrent engineering environment with inputs provided by users and or systems which may be located anywhere in the world provides a set of control information for coordinating movement of the design information through development and to release while providing dynamic tracking of the status of elements of the bills of materials in an integrated and coordinated activity control system utilizing a repository which can be implemented in the form of a database (relational, object oriented, etc.) or using a flat file system. Once a model is created and/or identified by control information design libraries hold the actual pieces of the design under control of the system without limit to the number of libraries, and providing for tracking and hierarchical designs which are allowed to traverse through multiple libraries.

Abstract: A design control system suitable for use in connection with the design of integrated circuits and other elements of manufacture having many parts which need to be developed in a concurrent engineering environment with inputs provided by users and or systems which may be located anywhere in the world providing a set of control information for coordinating movement of the design information through development and to release while providing dynamic tracking of the status of elements of the bills of materials in an integrated and coordinated activity control system utilizing a repository which can be implemented in the form of a database (relational, object oriented, etc.) or using a flat file system. Once a model is created and/or identified by control information design libraries hold the actual pieces of the design under control of the system without limit to the number of libraries, and providing for tracking and hierarchical designs which are allowed to traverse through multiple libraries.