Abstract: The present disclosure relates to regulation of macrophage activation by delivering of miRNAs, for example miR-125b or anti-miR-125b, to macrophages. For example, in some embodiments, macrophage activation can be elevated or reduced by administering miR-125b or anti-miR-125b oligonucleotides. Also disclosed are methods for promoting T cell activation and method for treating various disorders such as tumor and autoimmune diseases.

Abstract: The present disclosure relates to regulation of macrophage activation by delivering of miRNAs, for example miR-125b or anti-miR-125b, to macrophages. For example, in some embodiments, macrophage activation can be elevated or reduced by administering miR-125b or anti-miR-125b oligonucleotides. Also disclosed are methods for promoting T cell activation and method for treating various disorders such as tumor and autoimmune diseases.

Abstract: Systems and methods for measuring noise exposure associated with use of a wireless headset are presented. In one example, a transition from a wireless headset standby mode operation to a wireless headset active mode operation is identified. A stored noise dose measurement at the wireless headset is recalled, and a current noise dose measurement is calculated at the wireless headset for a duration of the active mode operation. A transition from the wireless headset active mode operation to the wireless headset standby mode operation is identified, and an updated noise dose measurement is recorded at the wireless headset.

Abstract: A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst counter starting from an externally applied starting address. The count direction of the counter is controlled by a counter control circuit that receives the LSB the next to least significant bit (“NLSB”) of the starting column address, as well as a signal indicative of the operating mode of the DRAM. In a serial operating mode, the counter control circuit causes the burst counter to increment when the LSB of the starting column address is “0” and to decrement when the LSB of the starting column address is “1”. In an interleave operating mode, the counter control circuit causes the burst counter to increment when the NLSB of the starting column address is “0” and to decrement when the NLSB of the starting column address is “1”.

Abstract: A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst counter starting from an externally applied starting address. The count direction of the counter is controlled by a counter control circuit that receives the LSB the next to least significant bit (“NLSB”) of the starting column address, as well as a signal indicative of the operating mode of the DRAM. In a serial operating mode, the counter control circuit causes the burst counter to increment when the LSB of the starting column address is “0” and to decrement when the LSB of the starting column address is “1”. In an interleave operating mode, the counter control circuit causes the burst counter to increment when the NLSB of the starting column address is “0” and to decrement when the NLSB of the starting column address is “1”.

Abstract: A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst counter starting from an externally applied starting address. The count direction of the counter is controlled by a counter control circuit that receives the LSB the next to least significant bit (“NLSB”) of the starting column address, as well as a signal indicative of the operating mode of the DRAM. In a serial operating mode, the counter control circuit causes the burst counter to increment when the LSB of the starting column address is “0” and to decrement when the LSB of the starting column address is “1”. In an interleave operating mode, the counter control circuit causes the burst counter to increment when the NLSB of the starting column address is “0” and to decrement when the NLSB of the starting column address is “1”.