Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

Abstract: A method of forming a microelectronic non-volatile memory cell, a non-volatile memory cell made according to the method, and a system comprising the non-volatile memory cell. The method comprises: providing a substrate; providing a pair of spaced apart isolation regions in the substrate, providing the pair comprising providing a buffer layer on the substrate; removing the buffer layer; providing a tunnel dielectric on a surface of the substrate after removing the buffer layer; providing a pair of device spacers on side walls of each of the isolation regions extending above the surface of the substrate; providing a floating gate on the tunnel dielectric; providing a source region and a drain region on opposite sides of the floating gate; providing an interpoly dielectric on the floating gate; and providing a control gate on the interpoly dielectric to yield the memory cell.