Patents by Inventor Steven Spangler

Steven Spangler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10546413
    Abstract: For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: January 28, 2020
    Assignee: INTEL CORPORATION
    Inventors: Liang Leon Peng, Steven Spangler
  • Publication number: 20190122418
    Abstract: For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Applicant: Intel Corporation
    Inventors: LIANG LEON PENG, STEVEN SPANGLER
  • Patent number: 10169907
    Abstract: For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: January 1, 2019
    Assignee: INTEL CORPORATION
    Inventors: Liang Leon Peng, Steven Spangler
  • Patent number: 10109069
    Abstract: A method includes computing an anisotropic filter with a major-axis and a minor-axis for a pixel to be displayed on screen-space, where the anisotropic filter is to be applied to corresponding MIPs on a texture map. Additionally, the method includes varying the length of the major-axis of the anisotropic filter based on the angle of the major-axis of anisotropy with respect to the screen space. Further, the method includes determining a number of texels from the texture map that are to be sampled in the anisotropic filter based on the length of the modified major-axis. The color of the pixel may be determined based on the texels sampled in the anisotropic filter.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Prosun Chatterjee, Larry Seiler, Steven Spangler
  • Publication number: 20170178350
    Abstract: A method for anisotropic filtering is provided herein. The method includes computing an anisotropic filter with a major-axis and a minor-axis for a pixel to be displayed on screen-space, wherein the anisotropic filter is to be applied to corresponding MIPs on a texture map. The method includes varying the length of the major-axis of the anisotropic filter based on the angle of the major-axis of anisotropy with respect to the screen space. The method includes determining a number of texels from the texture map that are to be sampled in the anisotropic filter based on the length of the modified major-axis. The method includes determining the color of the pixel based on the texels sampled in the anisotropic filter.
    Type: Application
    Filed: March 9, 2017
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Prosun Chatterjee, Larry Seiler, Steven Spangler
  • Patent number: 9619898
    Abstract: A method includes computing an anisotropic filter with a major-axis and a minor-axis for a pixel to be displayed on screen-space, wherein the anisotropic filter is to be applied to corresponding MIPs on a texture map. Additionally, the method includes varying the length of the major-axis of the anisotropic filter based on the angle of the major-axis of anisotropy with respect to the screen space. Further, the method includes determining a number of texels from the texture map that are to be sampled in the anisotropic filter based on the length of the modified major-axis. The color of the pixel may be determined based on the texels sampled in the anisotropic filter.
    Type: Grant
    Filed: December 28, 2013
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Prosun Chatterjee, Larry Seiler, Steven Spangler
  • Publication number: 20170098328
    Abstract: For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory.
    Type: Application
    Filed: May 6, 2016
    Publication date: April 6, 2017
    Inventors: LIANG LEON PENG, STEVEN SPANGLER
  • Patent number: 9489707
    Abstract: Embodiments described herein include a graphics processing unit. The graphics processing unit includes a plurality of execution units. The graphics processing unit also includes a plurality of sampler units. Each sampler unit corresponds to a sampler dispatch logic unit and at least one execution unit, and the sampler dispatch logic units are used to network the plurality of sampler units.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Hema Chand Nalluri, Joy Chandra, Prosun Chatterjee, Benjamin Pletcher, Yoav Harel, Steven Spangler
  • Patent number: 9367948
    Abstract: Multi-mode texture filters suitable for performing both bilinear filtering based on a fractional texture address and generating a weighted average of a group of texel values based on predetermined texel weighting coefficients as dependent on a filter mode signal. In embodiments, the weighted average may be accumulated over a variety of filter footprints. In embodiments, multi-mode texture filter logic includes a plurality of flexible filter blocks. In further embodiments, a pair of flexible filter blocks staged with each performing one lerp phase in the bilinear filter mode while a pair of flexible filter blocks in the flexible filter mode generate a weighted average over a pair of texels of a texel quad. In embodiments, each flexible filter block has a same microarchitecture, enabling an efficient utilization in either bilinear filter or flexible filter mode.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: June 14, 2016
    Assignee: INTEL CORPORATION
    Inventors: Liang Peng, Yoav Harel, Steven Spangler
  • Patent number: 9355489
    Abstract: For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: May 31, 2016
    Assignee: INTEL CORPORATION
    Inventors: Liang Peng, Steven Spangler
  • Patent number: 9355490
    Abstract: Texture filter logic suitable for determining a minimum or maximum texel value from a plurality of texel values associated with a filter footprint of arbitrary shape and size. In embodiments, logic circuitry includes a plurality of min/max comparison block stages is configured to perform comparisons and determine a min/max value of predetermined number of texel groups. In embodiments, the logic circuitry further includes a number of min/max collectors to accommodate filter footprints having more texel groups than the predetermined number accommodated by the min/max comparison block stages. Iterative comparisons may be performed until all texel groups in the given footprint have been compared. In further embodiments, the logic circuitry outputs four min/max texel values, which may then be further processed with a final comparison stages to arrive at one min/max value for a footprint.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: May 31, 2016
    Assignee: INTEL CORPORATION
    Inventors: Liang Peng, Steven Spangler, Yoav Harel
  • Publication number: 20150187090
    Abstract: A method for anisotropic filtering is provided herein. The method includes computing an anisotropic filter with a major-axis and a minor-axis for a pixel to be displayed on screen-space, wherein the anisotropic filter is to be applied to corresponding MIPs on a texture map. The method includes varying the length of the major-axis of the anisotropic filter based on the angle of the major-axis of anisotropy with respect to the screen space. The method includes determining a number of texels from the texture map that are to be sampled in the anisotropic filter based on the length of the modified major-axis. The method includes determining the color of the pixel based on the texels sampled in the anisotropic filter.
    Type: Application
    Filed: December 28, 2013
    Publication date: July 2, 2015
    Inventors: Prosun Chatterjee, Larry Seiler, Steven Spangler
  • Publication number: 20150130819
    Abstract: Texture filter logic suitable for determining a minimum or maximum texel value from a plurality of texel values associated with a filter footprint of arbitrary shape and size. In embodiments, logic circuitry includes a plurality of min/max comparison block stages is configured to perform comparisons and determine a min/max value of predetermined number of texel groups. In embodiments, the logic circuitry further includes a number of min/max collectors to accommodate filter footprints having more texel groups than the predetermined number accommodated by the min/max comparison block stages. Iterative comparisons may be performed until all texel groups in the given footprint have been compared. In further embodiments, the logic circuitry outputs four min/max texel values, which may then be further processed with a final comparison stages to arrive at one min/max value for a footprint.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Inventors: Liang Peng, Steven Spangler, Yoav Harel
  • Publication number: 20150130818
    Abstract: Multi-mode texture filters suitable for performing both bilinear filtering based on a fractional texture address and generating a weighted average of a group of texel values based on predetermined texel weighting coefficients as dependent on a filter mode signal. In embodiments, the weighted average may be accumulated over a variety of filter footprints. In embodiments, multi-mode texture filter logic includes a plurality of flexible filter blocks. In further embodiments, a pair of flexible filter blocks staged with each performing one lerp phase in the bilinear filter mode while a pair of flexible filter blocks in the flexible filter mode generate a weighted average over a pair of texels of a texel quad. In embodiments, each flexible filter block has a same microarchitecture, enabling an efficient utilization in either bilinear filter or flexible filter mode.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Inventors: Liang Peng, Yoav Harel, Steven Spangler
  • Publication number: 20150130826
    Abstract: For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Inventors: Liang Peng, Steven Spangler
  • Publication number: 20150091919
    Abstract: Embodiments described herein include a graphics processing unit. The graphics processing unit includes a plurality of execution units. The graphics processing unit also includes a plurality of sampler units. Each sampler unit corresponds to a sampler dispatch logic unit and at least one execution unit, and the sampler dispatch logic units are used to network the plurality of sampler units.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Hema Chand Nalluri, Joy Chandra, Prosun Chatterjee, Benjamin Pletcher, Yoav Harel, Steven Spangler
  • Publication number: 20070211068
    Abstract: Apparatus, systems and methods for implementing a reconfigurable floating point data filter are disclosed. For example, a method is disclosed, the method including configuring a texture filter in response to state data, where the state data specifying at least a data width of input texture data to be filtered, where the input texture data is in a floating point format, filtering the input texture data using the texture filter, and then reconfiguring the texture filter to be substantially fully utilized when the data width of the input texture data changes. Other implementations are also disclosed.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 13, 2007
    Inventors: Steven Spangler, Benjamin Pletcher
  • Publication number: 20050225557
    Abstract: A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.
    Type: Application
    Filed: June 7, 2005
    Publication date: October 13, 2005
    Inventors: Satyaki Koneru, Steven Spangler, Val Cook