Abstract: Clock recovery is used in a variety of communications network applications to enable nodes using different clocks to operate in an effectively synchronized manner. Example embodiments of the present invention include an apparatus and corresponding method for supporting client data transport with timing transparency and require neither a common clock to be available at both the ingress and egress sides of the connection nor overhead bytes to recover a client clock. Rather, client traffic clock recovery may be performed in example embodiments of the present invention entirely in the egress data path using the client data received from the ingress side after removing the clients signal from a higher level carrier signal.

Abstract: Clock recovery is used in a variety of communications network applications to enable nodes using different clocks to operate in an effectively synchronized manner. Example embodiments of the present invention include an apparatus and corresponding method for supporting client data transport with timing transparency and require neither a common clock to be available at both the ingress and egress sides of the connection nor overhead bytes to recover a client clock. Rather, client traffic clock recovery may be performed in example embodiments of the present invention entirely in the egress data path using the client data received from the ingress side after removing the clients signal from a higher level carrier signal.

Abstract: An automatic call distribution system includes an automatic call distribution network, a plurality of network terminations interconnectable with the automatic call distribution network using a first bus protocol, and an interface which is interconnectable with one of the first network terminations using the first bus protocol. The interface is operable for interfacing between the first bus protocol and a second bus protocol different than the first bus protocol, and a network termination functional module is interconnectable with the interface using the second bus protocol. An automatic call distributor interconnectable with a network termination using a first bus protocol is used by a method that includes the steps of coupling a bus converter with the network termination using the first bus protocol and coupling a network termination functional module with the bus converter using a second bus protocol different than the first bus protocol.

Abstract: A method and apparatus are provided for exchanging control information and voice data between an automatic call distributor and a line card of the automatic call distributor located at a site remote from the automatic call distributor through a wide-bandwidth communication channel. The method includes the step of allocating at least a first portion of the bandwidth of the wide-bandwidth communication channel for the control information and at least a second portion of the bandwidth to voice data. The interprocessor control information is transceived between a controller of the automatic call distributor and a controller of the line card under a packet data format within the first portion of the bandwidth allocated for control information and the voice data is transceived under a dedicated channel format within the second portion of the bandwidth between the automatic call distributor and line card.

Abstract: A microprocessor based system such as an automatic call distributor having a reset circuit to improve memory integrity of electronic memory is disclosed. The reset circuit includes a reset controller which receives an external reset signal that can be generated from a number of different sources. The external resent signal is synchronized with activity on a bus to produce an internal reset signal which is applied to the microprocessor to reset it after all pending requests for bus access are completed. The microprocessor is then reset, thus improving integrity of electronic memory.

Abstract: An interface circuit (100) for interfacing an electronic device, such as a microprocessor (102), operating at a device clock speed and a finite synchronous state machine (104) comprised of a D-type flip-flop (106) and a synchronous state machine (108), which are operating at a state clock speed, is provided. The device clock speed being capable of being greater than the state clock speed. The interface circuit.degree. (100) comprises an input circuit, which may comprise a first NAND gate (120), connected to a latch circuit which may comprise interconnected second and third NAND gates (124) and (126). The input circuit and latch circuit store an input signal (121) received from the electronic device and transmit the input signal (121) to the flip-flop (106) when the synchronous state machine (108) is ready to accept further input signals.

Abstract: Transmissions of synchronous digital data from a master control unit (50A) to a slave, network termination unit (50B) are via a pulse width modulated data stream including pulse width modulated binary code pulses (20, 22) with a pulse width modulated synchronization pulse (24) all of which have a preselected leading edge transition (28) at the same point in each cycle of a master clock signal. A clock signal is derived at the network termination unit (50B) from the received pulse width modulated binary data stream for decoding and for nonself-clocking, synchronous transmissions from the slave, network termination unit (50B) to the master, control unit (50A). The phase synchronization pulse (24) is employed to maintain phase sychronization between the transmission to and from the control unit (50A).

Abstract: A multi-requester arbitration circuit receives multiple asynchronous request signals and provides a first common timing signal from the request signals. A sample-and-hold circuit receives each of the request signals and produces corresponding output sample signals. The sample-and-hold circuit receives the first common timing signals. A time delay circuit produces a second timing signal from the first common timing signal. A storage circuit receives the output sample signals and produces corresponding output stored signals. The storage circuit receives the second timing signal. An arbitration circuit receives the output stored signals to select one of the request signals and provide at least an output control signal indicative thereof. The sample-and-hold circuit samples each of the request signals before the first common timing signals causes the sample-and-hold circuit to hold all request signals.