Abstract: A method of manufacturing a semiconductor device having an n by m array of cells (32) is described, where n and m are positive integers with n at least two. Individual cells (32) have perimeter regions (34) surrounding the cells, the perimeter regions between adjacent cells being common to the adjacent cells. The method includes the steps of determining the required width or widths of the perimeter regions and calculating the optimal aspect ratio of each cell to substantially minimize the total area of an n by m array of cells subject to the determined width or widths of the perimeter regions. Then, a semiconductor device having an n by m array of active having an aspect ratio substantially in accordance with the calculated ratio is made. The invention has application to a number of types of structure, including a double diode structure.

Abstract: Trench-gate field-effect transistors, for example power MOSFETs, are disclosed having trenched electrode configurations (11,23) that permit fast switching of the transistor, while also providing over-voltage protection for the gate dielectric (21) and facilitating manufacture. The gate electrode (11) comprising a semiconductor material of one conductivity type (n) is present in an upper part of a deeper insulated trench (20,21) that extends into a drain region (14,14a) of the transistor. A lower electrode (23) connected to a source (13,33) of the transistor is present in the lower part of the trench. This lower electrode (23) comprises a semiconductor material of opposite conductivity type (p) that adjoins the semiconductor material of the gate electrode (11) to form a p-n junction (31) between the gate electrode (11) and the lower electrode (23). The p-n junction (31) provides a protection diode (D) between the gate electrode (11) and the source (13,33).

Abstract: A transistor has a plurality of active zones, (22, 24) separated by separation regions (10). The zones include wide (22) and narrow (24) zones, and the wide zones are formed to be less susceptible to turning on a parasitic bipolar transistor, for example by omitting a source region (8) from the wide zones (22), so causing avalanche current to flow preferentially in the wide zones (22) which have a lesser susceptibility to turning on the parasitic bipolar transistor.

Abstract: A field effect transistor has source 12, body 10 and drain 8 formed on an insulating layer 4. Implant regions 40 are implanted under the source 12, laterally aligned with the source 12 by implantation through opening in the source mask. The ruggedness of the transistor may thereby be improved without affecting the doping in channel region 19.

Abstract: Trench-gate field-effect semiconductor devices, for example cellular power MOSFETs with compact geometries, comprise a semiconductor body (10) into which the trench-gate (11) extends from a surface-adjacent source region (13) through a channel-accommodating region (15) of opposite conductivity type (p) and into an underlying drain drift region (14). This invention provides the gate trench (20) with a width (w) that is smaller than its depth (d) and that tapers increasingly towards the bottom of the gate trench (20) to reduce the width (w) of the trench-gate (11) at a greater rate in the drain drift region (14) than in the channel-accommodating region (15).

Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11).

Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).

Abstract: A semiconductor rectifier includes an intermediate semiconductor region (29) extending between anode (9) and cathode (7) contacts. A trenched gate (19) with insulated sidewalls (15) and base (17) can deplete the intermediate region. However, a shield region (23) acts to shield the intermediate region (29) from the gate (19) to allow current to flow in dependence on the polarity of the voltage applied between anode and cathode contacts (9, 7).

Abstract: In the manufacture of trench-gate power MOSFETs, trenched Schottky rectifiers and other devices including a Schottky barrier, a guard region (15s), trenched insulated electrode (11s) and the Schottky barrier (80) are self-aligned with respect to each other by providing spacers (52) to form a narrow window (52a) at a wider window (51a) in a mask pattern (51, 51s) that masks where the Schottky barrier (80) is to be formed. The trenched insulated electrode (11s) is formed by etching a trench (20) at the narrow window (52a) and by providing insulating material (17) and then electrode material (11s) in the trench. The guard region (15s) is provided by introducing dopant (61) via the wider window (51a). The mask pattern (51, 51s) masks the underlying body portion against this dopant introduction and is sufficiently wide (y8) to prevent the dopant (61) from extending laterally into the area where the Schottky barrier (80) is to be formed.

Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. Thereby, the source region (13) and a contact window (18a) for a source electrode (33) can be self-aligned to a narrow trench (20) containing the trench-gate (11). Thereby, the channel-accommodating region (15) can also be provided after forming the trench-gate (11), and with very good control of its doping concentration (Na; p) adjacent to the trench (20). To achieve this control, its dopant is provided after removing the spacers (52) from the mask (51) so as to form a doping window (51b), which may also be used for the source dopant, adjacent to the trench-gate (11). A high energy dopant implant (61) or other doping process provides this channel dopant adjacent to the trench (20) and extending laterally below the mask (51, 51n).

Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11).

Abstract: A field effect transistor structure is formed with a body semiconductor layer (5) having source (9), body (7), drift region and drain (11). An upper semiconductor layer (21) is separated from the body by an oxide layer (17). The upper semiconductor layer (21) is doped to have a gate region (23) arranged over the body (7), a field plate region (25) arranged over the drift region 13 and at least one p-n junction (26) forming at least one diode between the field plate region (25) and the gate region (23). A source contact (39) is connected to both the source (9) and the field plate region (25).

Abstract: A field effect transistor structure is formed with a body semiconductor layer (1) having source (3), channel (7), drift region (9) and drain (5). An upper metallisation layer (15,17) is separated from the body by an oxide layer (11). The upper metallisation layer (15,17) has a gate region (15) arranged over the body and a field plate region (17) arranged over the drift region (9). A source contact (39) is connected to both the source (9) and the field plate region (25).

Abstract: A method of manufacturing a semiconductor device having an n by m array of cells (32) is described, where n and m are positive integers with n at least two. Individual cells (32) have perimeter regions (34) surrounding the cells, the perimeter regions between adjacent cells being common to the adjacent cells. The method includes the steps of determining the required width or widths of the perimeter regions and calculating the optimal aspect ratio of each cell to substantially minimize the total area of an n by m array of cells subject to the determined width or widths of the perimeter regions. Then, a semiconductor device having an n by m array of active having an aspect ratio substantially in accordance with the calculated ratio is made. The invention has application to a number of types of structure, including a double diode structure.