Abstract: The present disclosure discloses a chassis on which a plurality of daughter cards (circuits) can be implemented. The chassis includes a backplane; a plurality of slots attached to the backplane, the plurality of slots being configured to interface with a corresponding number of daughter cards; a switch attached to the backplane, the switch being configured to provide control inputs to each of the plurality of slots, wherein a subset of the plurality of slots are directly connected to the switch; and a processor attached to the backplane and connected to the switch, the processor being connected to a portion of the plurality of slots which are not directly connected to the switch, the processor being configured to receive a signal from the switch, modulate the signal, and transmit the modulated signal to a target slot of the portion of the plurality of slots to uniquely identify a daughter card in the target slot.

Abstract: A system and method for interfacing multiple SoCs (System on a Chip) to a single, shared memory device are provided. The system and method of the present disclosure provides for controlling the downloading of operating code to two or more SoC controller circuits sharing a memory containing the operating code and a common communications bus, where each controller is a master controller of the communications bus in normal operation. The system and method involves sequentially controlling access of each of the controller circuits to the communications bus to allow each device to separately download the common operating code. The system and method utilize a separate initializing circuit or device along with chaining the controllers together in a series such that each controller be held in a reset state to prevent communications bus access until the previous controller in the chain has completed its code download.