Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.

Abstract: A method of dicing a microelectronic device wafer comprising forming at least one trench in at least one dicing street on the microelectronic device wafer, wherein the trench prevents cracking and/or delamination problems in the interconnect layer of the microelectronic device wafers caused by a subsequent dicing by a wafer saw.

Abstract: According to one embodiment, a system is disclosed. The system includes a first integrated circuit (IC), an input/output (I/O) signal routing layer mounted below the first IC and a second IC mounted on the routing layer.

Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.

Abstract: Optoelectronic packages and methods to simultaneously couple an optoelectronic chip to a waveguide and substrate using conventional flux soldering processes are disclosed. A disclosed optoelectronic package includes a substrate, a waveguide mounted on the substrate, an optoelectronic chip having electrically conductive contacts coupled to the substrate via a metallic solder and an optical element located on the optoelectronic chip and coupled to the waveguide via an optical solder which protects the optical element during a metallic soldering of the optoelectronic chip to the substrate.

Abstract: Microelectronic packages including a microelectronic die disposed within a recess in a heat spreader and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the heat spreader to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die within the heat spreader. In another embodiment, a microelectronic die is disposed on a heat spreader which has a filler material disposed therearound and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the filler material to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die on the heat spreader.

Abstract: A microelectronic substrate including at least one microelectronic die disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic dice, or a plurality microelectronic dice encapsulated without the microelectronic substrate core. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

Abstract: An electrooptic assembly including a microelectronic package and an optical substrate, wherein the optical substrate includes a coupler and a waveguide. An electrooptic element is disposed to convert an electrical signal from the microelectronic package to an optical signal for transmission to the coupler and waveguide, and/or to receive an optical signal and convert it to an electrical signal for transmission to the microelectronic package.

Abstract: Microelectronic packages including a microelectronic die disposed within a recess in a heat spreader and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the heat spreader to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die within the heat spreader. In another embodiment, a microelectronic die is disposed on a heat spreader which has a filler material disposed therearound and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the filler material to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die on the heat spreader.

Abstract: A microelectronic package including at least one microelectronic die disposed within an opening in a microelectronic package core, wherein a liquid encapsulation material is injected with a dispensing needle within portions of the opening not occupied by the microelectronic dice. The encapsulation material is cure thereafter. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic package core to form the microelectronic package.

Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.

Abstract: A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and Si3N4, causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as H2 or NH3, depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.

Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.

Abstract: A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.

Abstract: A method of dicing a microelectronic device wafer comprising forming at least one trench in at least one dicing street on the microelectronic device wafer, wherein the trench prevents cracking and/or delamination problems in the interconnect layer of the microelectronic device wafers caused by a subsequent dicing by a wafer saw.

Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.

Abstract: A present invention includes a packaging technology that fabricates build-up layers on an encapsulated microelectronic die that has expanded area larger than that of the microelectronic die. An active surface of a microelectronic die is attached by an adhesive material to a protective film sheet to protect the active surface and to control the position of the microelectronic die during an encapsulation process. The protective film sheet has adhesive material substantially only in an area where the microelectronic die and/or a microelectronic package core are attached, or has the adhesive properties of the adhesive material diminished or eliminated in areas where an encapsulation material will be applied.

Abstract: A low cost microelectronic circuit package includes a single build up metallization layer above a microelectronic die. At least one die is fixed within a package core using, for example, an encapsulation material. A single metallization layer is then built up over the die/core assembly. The metallization layer includes a number of landing pads having a pitch that allows the microelectronic device to be directly mounted to an external circuit board. In one embodiment, the metallization layer includes a number of signal landing pads within a peripheral region of the layer and at least one power landing pad and one ground landing pad toward a central region of the layer.

Abstract: A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.

Abstract: A present invention includes a packaging technology that fabricates build-up layers on an encapsulated microelectronic die that has expanded area larger than that of the microelectronic die. An active surface of a microelectronic die is attached by an adhesive material to a protective film sheet to protect the active surface and to control the position of the microelectronic die during an encapsulation process. The protective film sheet has adhesive material substantially only in an area where the microelectronic die and/or a microelectronic package core are attached, or has the adhesive properties of the adhesive material diminished or eliminated in areas where an encapsulation material will be applied.