Abstract: An accelerator includes a memory, a compute zone to receive an encrypted workload downloaded from a tenant application running in a virtual machine on a host computing system attached to the accelerator, and a processor subsystem to execute a cryptographic key exchange protocol with the tenant application to derive a session key for the compute zone and to program the session key into the compute zone. The compute zone is to decrypt the encrypted workload using the session key, receive an encrypted data stream from the tenant application, decrypt the encrypted data stream using the session key, and process the decrypted data stream by executing the workload to produce metadata.

Abstract: According to some embodiments, a video block memory read request may be received from a processing unit. For example, a codec may request to access a macroblock of pixel information from a memory unit. The video block memory read request may then be translated into a plurality of memory access requests.

Abstract: According to some embodiments, encoded information associated with an image is received at a decoder. The encoded information may be decoded at the decoder to generate full-sized first image pixels representing a full-sized version of the image. Moreover, the full-sized pixels may be scaled at the decoder to generate scaled image pixels representing a scaled version of the image.

Abstract: According to some embodiments, encoded information associated with an image is received at a decoder. The encoded information may be decoded at the decoder to generate full-sized first image pixels representing a full-sized version of the image. Moreover, the full-sized pixels may be scaled at the decoder to generate scaled image pixels representing a scaled version of the image.

Abstract: According to some embodiments, a first bus may be monitored, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted.

Abstract: According to some embodiments, a first bus may be monitored, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted.

Abstract: According to some embodiments, a first bus may be monitored, via a first debug gate, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, via a second debug gate, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted.

Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. The semaphore control mechanism receives one or more semaphore modification requests from one or more requesting devices, identifies an ownership state of a semaphore corresponding to the one or more semaphore modification requests, arbitrates to identify modification request from a particular requesting device to succeed if the identified ownership state corresponds to the particular requesting device or if the identified ownership state corresponds to no ownership.

Abstract: The disclosure relates to a control mechanism for controlling access by multiple logical processors to shared resources on a common microchip. The processors attempt to reserve exclusive use of needed resources by updating a resource descriptor. The resource descriptor describes which logical processors have exclusive use of which resources. In order to update the resource descriptor, a logical processor must first obtain exclusive access to the resource descriptor by updating a semaphore.

Abstract: According to some embodiments, a video block memory read request may be received from a processing unit. For example, a codec may request to access a macroblock of pixel information from a memory unit. The video block memory read request may then be translated into a plurality of memory access requests.

Abstract: According to some embodiments, image information, including rows of pixels, may be determined. The image information may be associated with a plurality of image blocks, each image block including a subset of pixels from multiple rows. Moreover, a single row of pixels of the image information may span multiple image blocks. A first subset of pixels (from a first row of a first image block) may be stored into a memory unit. A second subset of pixels (from a second row of the first image block) may then be stored into the memory unit such that a first pixel of the second subset is stored proximate to a last pixel of the first subset.

Abstract: According to some embodiments, a first bus may be monitored, via a first debug gate, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, via a second debug gate, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted.

Abstract: According to some embodiments, encoded information associated with an image is received at a decoder. The encoded information may be decoded at the decoder to generate full-sized first image pixels representing a full-sized version of the image. Moreover, the full-sized pixels may be scaled at the decoder to generate scaled image pixels representing a scaled version of the image.

Abstract: Pipelining techniques to deinterlace video information are described. An apparatus may comprise deinterlacing logic to convert interlaced video data into deinterlaced video data using multiple processing pipelines. Each pipeline may process the interlaced video data in macroblocks. Each macroblock may comprise a set of working pixels from a current macroblock and supplemental pixels from a previous macroblock. Other embodiments are described and claimed.

Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively, or conditionally, acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. A machine check abort (MCA) handling mechanism is disclosed, which works with the semaphore control mechanism in the multiprocessor to provide improved system availability and reliability. The MCA handling mechanism provides for synchronization of multiple processors and shared resources and for timely execution resumption within the processors that remain on-line.

Abstract: A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first bus agent and the second bus agent assert their respective bus request signals in a single clock cycle. Once a bus arbitration event is detected, bus ownership may be granted to both the first bus agent and the second bus agent, when the first bus agent and the second bus agent have different grant-to-valid latencies. In the embodiment, heterogeneous bus agents may coexist on a bus without requiring wasted or unused bus cycles following establishment of bus ownership. Other embodiments are described and claimed.

Abstract: Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.

Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. A machine check abort (MCA) handling mechanism is disclosed, which works with the semaphore control mechanism in the multiprocessor to provide improved system availability and reliability. The MCA handling mechanism provides for synchronization of multiple processors and shared resources and for timely execution resumption within the processors that remain on-line.