Abstract: In a large semiconductor memory having multiple memory modules that are addressable by a logical page address and a word address within each page, a technique for automatically testing the modules to establish a pool of good modules; then allocating each logical page of memory to a group of modules, with each module in the group being assigned to a particular bit position in all of the data words in the page. After allocation of each page, the modules in the page are tested in various ways to verify that they are fully functional. Modules not passing any of the tests are replaced by others from the pool of good modules. If the pool is exhausted, a partial page is de-allocated. Tests performed on the modules making up a logical page include a random access memory test, a test on bus connections to each module, and tests on the other major components of each module.

Abstract: A very large memory structure in which the extent and capacitive loading of global buses are reduced by an arrangement in which global data, address and control buses are connected to column buses through a column disable block for each column of memory modules. The column disable blocks also provide for selection of only a subset of data lines for connection between the global data bus and an associated column data bus. Further, a column disable register in each column disable block permits output from the column data bus to be selectively ignored on the basis of bit position. The column disable registers are uniquely addressable by column, for the selective disablement of column data bus lines. In the described embodiment of the invention, the global buses are triply redundant and the column disable blocks also include voting circuitry for processing of signals from the global buses.

Abstract: An improved memory module structure for use in a large memory in which, before operational use, the memory modules are tested and configured by a process that requires storing logical page addresses into a page register in each module. In this module, page address data are input to the page register from a data input line to the module. Since there is a separate data input line for each module in a column of such modules, and since the data input lines are not used to carry data to the memory in a test and configuration mode, the data input lines can be used to supply page address data simultaneously to the page registers of an entire column of modules. This avoids having to address each module in the column individually, and reduces testing an configuration time by a factor equal to the number of modules in a column. The complexity of each module is also reduced by obviating the need for individual module addressing in the test mode.

Abstract: A semiconductor memory structure having multiple memory modules that can be assigned or reassigned to serve in different logical memory locations, to obviate fault conditions detected in one or more modules. A logical addressing scheme treats the memory as having P pages, each with N multibit memory words. The memory modules are each 1.times.N bits in size and each module provides one bit of memory at the same bit position in every word in the page. This minimizes the effect of radiation damage, since a damaged module will affect only one bit in each word, and one missing bit in a word can be reconstructed using conventional error detection and correction techniques. The memory structure includes a memory mapping unit, which yields a set of module assignments for each page of memory.