Patents by Inventor Steven Van Aerde
Steven Van Aerde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230230833Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.Type: ApplicationFiled: March 28, 2023Publication date: July 20, 2023Inventors: Dieter Pierreux, Steven van Aerde, Bert Jongbloed, Kelly Houben, Werner Knaepen, Wilco Verweij
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Publication number: 20230220588Abstract: A method of forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing a semiconductor processing apparatus. This semiconductor processing apparatus comprises a process chamber and a carousel for stationing a wafer boat before or after processing in the process chamber. The method further comprises loading the wafer boat into the process chamber, the wafer boat comprising the plurality of substrates. The method further comprises processing the plurality of substrates in the process chamber, thereby forming, on the plurality of substrates, the epitaxial stack. This epitaxial stack has a pre-determined thickness. The processing comprises unloading the wafer boat, one or more times, from the process chamber to the carousel until the epitaxial stack reaches the pre-determined thickness.Type: ApplicationFiled: January 11, 2023Publication date: July 13, 2023Inventors: Steven Van Aerde, Wilco Verweij, Dieter Pierreux, Kelly Houben, Bert Jongbloed, Peter Westrom
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Publication number: 20230223255Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer.Type: ApplicationFiled: January 11, 2023Publication date: July 13, 2023Inventors: Steven Van Aerde, Wilco Verweij, Bert Jongbloed, Dieter Pierreux, Kelly Houben, Rami Khazaka, Frederick Aryeetey, Peter Westrom, Omar Elleuch, Caleb Miskin
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METHOD AND WAFER PROCESSING FURNACE FOR FORMING AN EPITAXIAL STACK OF SEMICONDUCTOR EPITAXIAL LAYERS
Publication number: 20230223258Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing plurality of substrates to a process chamber. A plurality of deposition cycles are executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial comprises a plurality of epitaxial pairs, each pair comprising a first epitaxial layer and a second epitaxial layer. The deposition cycle comprises a first deposition pulse and a second deposition pulse.Type: ApplicationFiled: January 11, 2023Publication date: July 13, 2023Inventors: Dieter Pierreux, Kelly Houben, Steven Van Aerde, Wilco Verweij, Bert Jongbloed, Charles Dezelah -
Patent number: 11646204Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.Type: GrantFiled: June 21, 2021Date of Patent: May 9, 2023Assignee: ASM IP Holding B.V.Inventors: Dieter Pierreux, Steven van Aerde, Bert Jongbloed, Kelly Houben, Werner Knaepen, Wilco Verweij
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Publication number: 20230127833Abstract: A method and a wafer processing furnace for forming a doped polysilicon layer on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing a plurality of substrates to a process chamber. It also comprises executing a deposition cycle comprising providing a silicon-containing precursor to the process chamber thereby depositing, on the plurality of substrates, an undoped silicon layer until a pre-determined thickness is reached and providing the process chamber with a flow of a dopant precursor gas without providing the silicon-containing precursor to the process chamber. The method also comprises performing a heat treatment process, thereby forming the doped polysilicon layer.Type: ApplicationFiled: October 20, 2022Publication date: April 27, 2023Inventors: Steven Van Aerde, Juan Su
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Publication number: 20230084173Abstract: A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole by dry etching. In this way 3-D NAND device may be provided.Type: ApplicationFiled: November 18, 2022Publication date: March 16, 2023Inventors: Dieter Pierreux, Steven van Aerde, Bert Jongbloed
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Patent number: 11594450Abstract: A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole by dry etching. In this way 3-D NAND device may be provided.Type: GrantFiled: August 17, 2020Date of Patent: February 28, 2023Assignee: ASM IP Holding B.V.Inventors: Dieter Pierreux, Steven van Aerde, Bert Jongbloed
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Patent number: 11501968Abstract: Method for filling a gap, comprising providing in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material; depositing a silicon precursor in the gap.Type: GrantFiled: November 9, 2020Date of Patent: November 15, 2022Assignee: ASM IP Holding B.V.Inventors: Dieter Pierreux, Anna Trovato, Kelly Houben, Steven van Aerde, Bert Jongbloed, Wilco A. Verweij
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Patent number: 11230766Abstract: The invention relates to a substrate processing apparatus comprising a reaction chamber provided with a substrate rack for holding a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the plurality of substrates. The apparatus may have an illumination system constructed and arranged to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.Type: GrantFiled: March 29, 2018Date of Patent: January 25, 2022Assignee: ASM IP Holding B.V.Inventors: Dieter Pierreux, Cornelis Thaddeus Herbschleb, Werner Knaepen, Bert Jongbloed, Steven Van Aerde, Kelly Houben, Theodorus Oosterlaken, Chris de Ridder, Lucian Jdira
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Publication number: 20210407789Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.Type: ApplicationFiled: June 21, 2021Publication date: December 30, 2021Inventors: Dieter Pierreux, Steven van Aerde, Bert Jongbloed, Kelly Houben, Werner Knaepen, Wilco Verweij
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Publication number: 20210151315Abstract: Method for filling a gap, comprising providing in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material; depositing a silicon precursor in the gap.Type: ApplicationFiled: November 9, 2020Publication date: May 20, 2021Inventors: Dieter Pierreux, Anna Trovato, Kelly Houben, Steven van Aerde, Bert Jongbloed, Wilco A. Verweij
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Publication number: 20210057275Abstract: A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole by dry etching. In this way 3-D NAND device may be provided.Type: ApplicationFiled: August 17, 2020Publication date: February 25, 2021Inventors: Dieter Pierreux, Steven van Aerde, Bert Jongbloed
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Publication number: 20190301014Abstract: The invention relates to a substrate processing apparatus comprising a reaction chamber provided with a substrate rack for holding a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the plurality of substrates. The apparatus may have an illumination system constructed and arranged to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Inventors: Dieter Pierreux, Cornelis Thaddeus Herbschleb, Werner Knaepen, Bert Jongbloed, Steven Van Aerde, Kelly Houben, Theodorus Oosterlaken, Chris de Ridder, Lucian Jdira
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Publication number: 20070141812Abstract: A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with the flow of the dopant precursor or separately from the flow of the dopant precursor. Surprisingly, deposition rate is independent of dopant precursor flow, while dopant incorporation linearly increases with the dopant precursor flow.Type: ApplicationFiled: December 14, 2006Publication date: June 21, 2007Inventors: Peter Zagwijn, Theodorus Gerardus Oosterlaken, Steven Van Aerde, Pamela Fischer
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Publication number: 20070134887Abstract: The invention relates to a of manufacturing a silicon dioxide layer of low roughness, that includes depositing a layer of silicon dioxide over a substrate by a low pressure chemical vapour deposition (LPCVD) process, the deposition process employing simultaneously a flow of tetraethylorthosilicate (TEOS) as the source material for the film deposition and a flow of a diluant gas that it not reactive with TEOS, so that the diluant gas/TEOS flow ratio is between 0.5 and 100; and annealing the silicon dioxide layer at a temperature between 600° C. and 1200° C., for a duration between 10 minutes and 6 hours.Type: ApplicationFiled: February 22, 2007Publication date: June 14, 2007Inventors: Konstantin Bourdelle, Nicolas Daval, Ian Cayrefourcq, Steven Van Aerde, Marinus De Blank, Cornelius Van Der Jeugd