Patents by Inventor Steven Vitale

Steven Vitale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11846622
    Abstract: Provided are aptamer-functionalized graphene sensors, capable of detecting various analytes, including toxins, at comparatively low concentrations. Also provided are methods of fabricating and using such aptamer-functionalized graphene sensors.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: December 19, 2023
    Assignee: The Trustees of the University of Pennsylvania
    Inventors: Alan T. Johnson, Jr., Jinglei Ping, Steven Vitale, Chengyu Wen
  • Patent number: 10418350
    Abstract: A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 17, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Patent number: 10079224
    Abstract: A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corresponding method for fabricating a semiconductor structure is also provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 18, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Patent number: 9780075
    Abstract: A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 3, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Publication number: 20170200700
    Abstract: A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Application
    Filed: August 11, 2015
    Publication date: July 13, 2017
    Applicant: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Publication number: 20170162550
    Abstract: A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corres ponding method for fabricating a semiconductor structure is also provided.
    Type: Application
    Filed: August 11, 2015
    Publication date: June 8, 2017
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Publication number: 20170162507
    Abstract: A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Application
    Filed: August 11, 2015
    Publication date: June 8, 2017
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Patent number: 9035399
    Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: May 19, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Joe G. Tran
  • Patent number: 8574980
    Abstract: A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: November 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Craig H. Huffman
  • Publication number: 20130056641
    Abstract: Thermal Neutron Detector. The detector includes at least one semiconductor transistor within a circuit for monitoring current flowing through the semiconductor transistor. A film of gadolinium-containing material covers the semiconductor transistor whereby thermal neutrons interacting with the gadolinium-containing material generate electrons that induce a change in current flowing through the semiconductor transistor to provide neutron detection.
    Type: Application
    Filed: June 5, 2012
    Publication date: March 7, 2013
    Applicant: Massachusetts Institute of Technology
    Inventors: Steven A. Vitale, Pascale Gouker
  • Publication number: 20100176462
    Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
    Type: Application
    Filed: March 25, 2010
    Publication date: July 15, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Joe G. Tran
  • Patent number: 7727842
    Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: June 1, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Joe G. Tran
  • Publication number: 20090321846
    Abstract: A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate.
    Type: Application
    Filed: September 8, 2009
    Publication date: December 31, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Craig H. Huffman
  • Publication number: 20090057776
    Abstract: A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate.
    Type: Application
    Filed: April 27, 2007
    Publication date: March 5, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Craig H. Huffman
  • Publication number: 20080265344
    Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Joe G. Tran
  • Publication number: 20070212864
    Abstract: A method for manufacturing a semiconductive device comprising forming a mask for a semiconductive device structure over a layer of a semiconductor substrate and partially etching the layer to form lateral and vertical surfaces. Thicknesses of one to several atomic diameters of atoms that comprise said layer are removed from the lateral surfaces and the vertical surfaces that are located under the mask to form a target dimension of a semiconductive device structure.
    Type: Application
    Filed: March 10, 2006
    Publication date: September 13, 2007
    Applicant: Texas Instruments Inc.
    Inventor: Steven Vitale
  • Publication number: 20070196961
    Abstract: A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension.
    Type: Application
    Filed: February 22, 2006
    Publication date: August 23, 2007
    Inventor: Steven Vitale
  • Patent number: 7244642
    Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: July 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Steven A. Vitale, Hyesook Hong, Freidoon Mehrad
  • Publication number: 20070161245
    Abstract: In accordance with the invention, there are methods of making an integrated circuit, an integrated circuit device, and a computer readable medium. A method can comprise forming a first layer over a semiconductor substrate, forming a first mask layer over the semiconductor substrate, and using the first mask layer to pattern first features. The method can also include forming a second mask layer over the first features, using the second mask layer to pattern portions of the first features, removing the second mask layer, and removing the first mask layer.
    Type: Application
    Filed: January 6, 2006
    Publication date: July 12, 2007
    Inventors: Benjamen Rathsack, James Blatchford, Steven Vitale
  • Publication number: 20070099424
    Abstract: According to various embodiments, methods to eliminate high stress areas in a mask during a gate trim etch are provided. High stress areas can include, for example, gate regions that are anchored at only one end. The exemplary methods can include the use of a double pattern layout, for example, separating printing and etching of a pattern specific geometry in the mask into two or more portions.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 3, 2007
    Inventors: Benjamen Rathsack, James Blatchford, Steven Vitale