Abstract: An apparatus and method is provided for removing smudges (506, 706, 806, 906) including oils and dust from portable electronic displays. The apparatus comprises a display device (110, 150, 500, 700, 800, 900, 1000) positioned within a housing (102, 104, 808), comprising a transparent cover (302, 502, 702, 802, 902, 1002) having a surface (508, 908) viewable through an opening in the housing (102, 104, 808) and a susceptibility to receiving contaminants (506, 706, 806, 906). A vibration device (504, 704, 804, 904, 1004) is positioned against the transparent cover (302, 502, 702, 802, 902, 1002) to provide motion (510) in a direction parallel to the surface, thereby causing the contaminants to move (708) across the surface (508, 908). The contaminants (506, 706, 806, 906) may then be hidden by the housing (102, 104, 808) or ejected by a motion (912) perpendicular to the surface by another vibrating device (911).

Abstract: A transparent display cover (100) and a method of forming such includes forming (204) a transparent polymer material (104) having a thickness between 0.2 and 38 micrometers on a glass material (102) and disposing (216) one of the materials (106) selected from the group consisting of an antireflective coating and a vacuum metallized coating on the transparent polymer material (104). The transparent polymer material (104) may comprise one of a polyimide, siloxane, polyurethane, polyester, polycarbonate, and polyethylene applied (204) by spin coat or meniscus with a thickness of less than 38 micrometers.

Abstract: An apparatus and method is provided for removing smudges (506, 706, 806, 906) including oils and dust from portable electronic displays. The apparatus comprises a display device (110, 150, 500, 700, 800, 900, 1000) positioned within a housing (102, 104, 808), comprising a transparent cover (302, 502, 702, 802, 902, 1002) having a surface (508, 908) viewable through an opening in the housing (102, 104, 808) and a susceptibility to receiving contaminants (506, 706, 806, 906). A vibration device (504, 704, 804, 904, 1004) is positioned against the transparent cover (302, 502, 702, 802, 902, 1002) to provide motion (510) in a direction parallel to the surface, thereby causing the contaminants to move (708) across the surface (508, 908). The contaminants (506, 706, 806, 906) may then be hidden by the housing (102, 104, 808) or ejected by a motion (912) perpendicular to the surface by another vibrating device (911).

Abstract: An optical waveguide structure (10) is provided. The optical waveguide structure (10) has a monocrystalline substrate (12), an amorphous interface layer (14) overlying the monocrystalline substrate (12) and an accommodating buffer layer (16) overlying the amorphous interface layer (14). An optical waveguide layer (20) overlies the accommodating buffer layer (16).

Abstract: An optical waveguide structure (10) is provided. The optical waveguide structure (10) has a monocrystalline substrate (12), an amorphous interface layer (14) overlying the monocrystalline substrate (12) and an accommodating buffer layer (16) overlying the amorphous interface layer (14). An optical waveguide layer (20) overlies the accommodating buffer layer (16).

Abstract: High quality epitaxial layers of monocrystalline piezoelectric materials and compound semiconductor materials can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. An integrated circuit including at least one surface acoustic wave device can be formed in and over the high quality epitaxial layers.

Abstract: A field emission device (100, 200, 300, 400, 500) includes a substrate (110, 210, 310, 410, 510), a cathode (115, 215, 315, 415, 515) formed thereon, a plurality of electron emitters (170, 270, 370, 470, 570) and a plurality of gate electrodes (150, 250, 350, 450, 550) proximately disposed to the plurality of electron emitters (170, 270, 370, 470, 570) for effecting electron emission therefrom, a dielectric layer (140, 240, 340, 440, 540) having a major surface (143, 243, 343, 443, 543), a surface passivation layer (190, 290, 390, 490, 590) formed on the major surface (143, 243, 343, 443, 543), and an anode (180, 280, 380, 480, 580) spaced from the gate electrodes (250, 350, 450, 550).

Abstract: A field emission device (100, 150) includes a cathode plate (102, 180) having electron emitters (116), an anode plate (104, 170) having a phosphor (107, 207, 307, 407) activated by electrons (119) emitted by electron emitters (116), and a vacuum bridge focusing structure (118, 158, 218, 318) for focusing electrons (119) emitted by electron emitters (116). Vacuum bridge focusing structure (118, 158, 218, 318) has landings (121, 122, 221, 322), which are attached to cathode plate (102, 180), and further has bridges (120, 220, 320), which extend above and beyond landings (121, 122, 221, 322, 421) to provide a self-supporting structure that is spaced apart from cathode plate (102, 180).

Abstract: A method for fabricating an array of conical electron emitters (410) includes the steps of: (i) positioning a collimator (160), including a plurality of collimation cells (162) having hexagonal cross-sections, between a substrate (155) having emitter wells (130) and a target (170) made from the emitter material, (ii) sputtering the target (170) so that it is partially collimated by the collimator (160), (iii) moving the substrate (155) within a plane defined by the substrate (155) so that the emitter wells (130) follow an emitter well path (220) which forms a 15.degree. path angle (235) with respect to a reference line (240) of the collimator (160).

Abstract: A first layer of non-magnetic material is positioned on a layer of an oxide of a magnetic material (e.g. NiO). First and second layers of magnetic material are stacked in parallel, overlying relationship and separated by a second layer of non-magnetic material sandwiched therebetween to form a magnetic memory cell. The magnetic memory cell is positioned on the first layer of nonmagnetic material so as to sandwich the first nonmagnetic layer between the oxide and the first magnetic layer of the cell. The first layer of non-magnetic material has a thickness (e.g. approximately 7 .ANG.) which prevents the oxide from pinning the first layer of magnetic material and adapts the first layer of magnetic material to the layer of oxide so as to increase the GMR ratio of the magnetic memory cell.

Abstract: A plurality of edge emitters in a FED array include a plate shaped substrate having parallel, laterally spaced apart grooves formed in a first surface and parallel, laterally spaced apart grooves formed in the opposite surface so that each second groove crosses each first groove at an angle. The combined depths of the grooves is greater than the thickness of the plate substrate so that an opening is formed through the substrate at each point where a second groove crosses a first groove. Gate metal is deposited on the surfaces in the openings and emitter material is deposited on the lands of the first surface to form FED emitters in each opening.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Abstract: A method of reducing the leakage current of a III-V compound semiconductor device (10) includes providing the device with a confinement layer having two sections (13, 14). A first section (14) has a higher doping concentration than a second section (13). An energy barrier that confines minority carriers to an active layer (12) of the device (10) is formed by diffusing a dopant into a portion of the active layer (12) and the two sections (13, 14) of the confinement layer. During the diffusion, the conductivity type of a portion of the lower doped second section (13) is inverted while the higher doped first section (14) is not inverted.