Abstract: A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.

Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

Abstract: A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.

Abstract: A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.

Abstract: A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is indicative of stored information and different write voltage levels across the pair of memory element electrodes are employed to store nonvolatile information. The array has at least one enhanced functionality portion that performs operations selected from the group consisting of reference, error correction, device specific storage, defect mapping tables, and redundancy.

Abstract: A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.

Abstract: A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

Abstract: A cross point array and peripheral circuitry that accesses the cross point array. The peripheral circuitry receives a supply voltage of approximately 1.8 volts or less, generates voltages of a magnitude not more than approximately 3 volts, and senses current that is indicative of a nonvolatile memory state.

Abstract: A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

Abstract: Layouts of driver sets in a cross point memory array. Since both terminals of a memory cell in a cross point structure are typically used for selection purposes, dedicated driver sets are typically required for both x and y directions. By fabricating the cross point array above the driver circuitry, several different driver set layouts can be utilized that allow for varying designs.

Abstract: A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.

Abstract: A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally doping a multi-resistive state material to modify the electrical properties can, therefore, be desirable.

Abstract: A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.

Abstract: Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if the x-direction drivers are positioned in the middle of the x-direction conductive array lines and the y-direction drivers are positioned in the middle of the y-direction conductive array lines, the access time will be improved.

Abstract: A memory array with components that can withstand high temperature fabrication is provided. Some memory materials require high temperature process steps in order to achieve desired properties. During fabrication, a memory material is deposited on structures that may include metal lines and barrier layers. Such structures are then exposed to the high temperature processing steps and should be resistant to such temperatures.

Abstract: A 2-terminal trapped charge memory device is disclosed with voltage switchable multi-level resistance. The trapped charge memory device has a trapped charge memory body sandwiched between two electrodes. The trapped charge memory body can be made of a variety of semiconducting or insulating materials of single-crystalline, poly-crystalline or amorphous structure while containing current carrier traps whose respective energy levels and degrees of carrier occupancy, modifiable by the height and width of an applied write voltage pulse, determine the resistance. The mechanism of modification can be through carrier tunneling, free carrier capturing, trap-hopping conduction or Frenkel-Poole conduction. The current carrier traps can be created with dopant varieties or an initialization procedure.

Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines being uniquely defined. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage can be approximately equal to the average of the first select voltage and the second select voltage.

Abstract: Line drivers that use minimal metal layers. Line driver connections typically need to be made to various other peripheral circuits. Although multiple metal layers could be used to make all the necessary connections, it is desirable to use the fewest metal layers possible. By keeping all y-direction lines on a first layer, and most of the x-direction lines on a second layer, only two metal layers are required. Additionally, an array cut could be used that allows line drivers to reach upper conductive array lines.