Patents by Inventor Steven W. Mittl
Steven W. Mittl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10170460Abstract: Embodiments of the present invention provide systems and methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.Type: GrantFiled: February 28, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Alain F. Loiseau, Steven W. Mittl, Andreas D. Stricker
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Publication number: 20180247932Abstract: Embodiments of the present invention provide computer system for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.Type: ApplicationFiled: February 26, 2018Publication date: August 30, 2018Inventors: Alain F. Loiseau, Steven W. Mittl, Andreas D. Stricker
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Publication number: 20180247931Abstract: Embodiments of the present invention provide a computer program product for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.Type: ApplicationFiled: February 19, 2018Publication date: August 30, 2018Inventors: Alain F. Loiseau, Steven W. Mittl, Andreas D. Stricker
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Publication number: 20180247930Abstract: Embodiments of the present invention provide systems and methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.Type: ApplicationFiled: February 28, 2017Publication date: August 30, 2018Inventors: Alain F. Loiseau, Steven W. Mittl, Andreas D. Stricker
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Patent number: 9978743Abstract: Embodiments of the present invention provide methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.Type: GrantFiled: September 25, 2017Date of Patent: May 22, 2018Assignee: International Business Machines CorporationInventors: Alain F. Loiseau, Steven W. Mittl, Andreas D. Stricker
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Patent number: 9310418Abstract: Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured current transients are fit to an equation representing a time dependence for stress induced leakage currents. The measured current transients are corrected based upon stress currents computed from the equation to define corrected current transients.Type: GrantFiled: November 7, 2014Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: Steven W. Mittl, Ernest Y. Wu
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Patent number: 9310424Abstract: A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.Type: GrantFiled: February 25, 2013Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Ronald J. Bolam, Alan J. Drake, Charles R. Lefurgy, Barry P. Linder, Steven W. Mittl, Karthick Rajamani
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Publication number: 20150061724Abstract: Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured current transients are fit to an equation representing a time dependence for stress induced leakage currents. The measured current transients are corrected based upon stress currents computed from the equation to define corrected current transients.Type: ApplicationFiled: November 7, 2014Publication date: March 5, 2015Inventors: Steven W. Mittl, Ernest Y. Wu
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Patent number: 8937487Abstract: Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured current transients are fit to an equation representing a time dependence for stress induced leakage currents. The measured current transients are corrected based upon stress currents computed from the equation to define corrected current transients.Type: GrantFiled: May 27, 2011Date of Patent: January 20, 2015Assignee: International Business Machines CorporationInventors: Steven W. Mittl, Ernest Y. Yu
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Publication number: 20140244212Abstract: A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Applicant: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Ronald J. Bolam, Alan J. Drake, Charles R. Lefurgy, Barry P. Linder, Steven W. Mittl, Karthick Rajamani
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Patent number: 8713490Abstract: A mechanism is provided for mitigating aging of a set of components in the data processing system. A modeled age of a component in the set of components is identified. A desired aging requirement for the component is identified and a determination is made as to whether the modeled age of the component is greater than the desired age of the component. Responsive to the modeled age of the component being greater than the desired age of the component, a policy is implemented to mitigate the aging of the component.Type: GrantFiled: February 25, 2013Date of Patent: April 29, 2014Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Ronald J. Bolam, Alan J. Drake, Charles R. Lefurgy, Barry P. Linder, Steven W. Mittl, Karthick Rajamani
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Patent number: 8587383Abstract: A method establishes an initial voltage in a ring oscillator and a logic circuit of an integrated circuit device. Following this, the method enables the operating state of the ring oscillator. After enabling the operating state of the ring oscillator, the method steps up to a stressing voltage in the ring oscillator. The initial voltage is approximately one-half the stressing voltage. The stressing voltage creates operating-level stress within the ring oscillator. The method measures the operating-level frequency within the ring oscillator using an oscilloscope (after stepping up to the stressing voltage).Type: GrantFiled: December 7, 2011Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: David G. Brochu, Jr., Dimitris P. Ioannou, Travis S. Merrill, Steven W. Mittl
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Publication number: 20130147562Abstract: A method establishes an initial voltage in a ring oscillator and a logic circuit of an integrated circuit device. Following this, the method enables the operating state of the ring oscillator. After enabling the operating state of the ring oscillator, the method steps up to a stressing voltage in the ring oscillator. The initial voltage is approximately one-half the stressing voltage. The stressing voltage creates operating-level stress within the ring oscillator. The method measures the operating-level frequency within the ring oscillator using an oscilloscope (after stepping up to the stressing voltage).Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Applicant: Internatinal Business Machines CorporationInventors: David G. Brochu, JR., Dimitris P. Ioannou, Travis S. Merrill, Steven W. Mittl
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Publication number: 20120303303Abstract: Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured current transients are fit to an equation representing a time dependence for stress induced leakage currents. The measured current transients are corrected based upon stress currents computed from the equation to define corrected current transients.Type: ApplicationFiled: May 27, 2011Publication date: November 29, 2012Applicant: International Business Machines CorporationInventors: Steven W. Mittl, Ernest Y. Wu
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Patent number: 6770501Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.Type: GrantFiled: October 23, 2002Date of Patent: August 3, 2004Assignee: International Business Machines CorporationInventors: Jay Burnham, Eduard A. Cartier, Thomas G. Ference, Steven W. Mittl, Anthony K. Stamper
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Publication number: 20030102529Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.Type: ApplicationFiled: October 23, 2002Publication date: June 5, 2003Inventors: Jay Burnham, Eduard A. Cartier, Thomas G. Ference, Steven W. Mittl, Anthony K. Stamper
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Patent number: 6521977Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.Type: GrantFiled: January 21, 2000Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Jay Burnham, Eduard A. Cartier, Thomas G. Ference, Steven W. Mittl, Anthony K. Stamper
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Patent number: 6307250Abstract: An electronic switch circuit switches out bad decoupling capacitors on a high speed integrated circuit chip. The circuit comprises a control device that operates in the subthreshold or off device state to detect leakage in a decoupling capacitor. This control device operates in a low impedance state if the capacitor is good and in a high impedance sate if the capacitor is bad. A feedback circuit is connected from an internal node of the capacitor to a gate of the control device so that once a state of the capacitor is detected it can be stored on the gate of the control device. A single external signal source shared by a group of capacitors activates the control device to detect leakage in the capacitor. The circuit operates to switch out capacitors that fail during normal operation.Type: GrantFiled: April 1, 1996Date of Patent: October 23, 2001Assignee: International Business Machines CorporationInventors: Byron L. Krauter, Chung H. Lam, Linda A. Miller, Steven W. Mittl, Robert F. Sechler, Scott R. Stiffler, Donald L. Thompson
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Patent number: 6252275Abstract: A non-volatile random access memory (NVRAM) structure comprising an injector element in a single crystal silicon substrate; an insulator layer over the substrate; a silicon-on-insulator (SOI) layer over the insulator layer; and a sensing element in the SOI layer overlying the injector element. The NVRAM structure may further comprise a gate above the SOI layer, a floating gate in the insulator layer, or both.Type: GrantFiled: January 7, 1999Date of Patent: June 26, 2001Assignee: International Business Machines CorporationInventors: John M. Aitken, Steven W. Mittl, Alvin W. Strong
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Patent number: 5982225Abstract: A circuit actively monitors and measures the amount of MOS device degradation due to, for example, the hot electron effect, and makes compensatory adjustments to device voltage levels or clock speed to maintain desired levels of functionality and performance. Monitoring can be done separately for NFET and PFET devices to selectively adjust for different degradation rates between the two. In operation, the monitor circuit compares the performance of a stressed device to a reference device, that is, an unstressed device which has not been degraded by the hot-electron effect. The monitor circuit outputs a signal indicating the amount of device degradation. This signal is used to adjust the supply voltage to that device or to the chip or otherwise compensate for the degradation. The monitor circuit can be formed on-chip or off-chip.Type: GrantFiled: August 6, 1997Date of Patent: November 9, 1999Assignee: International Business Machines CorporationInventors: Timothy E. Forhan, Terence B. Hook, Steven W. Mittl, Edward J. Nowak, Madhu Sayala, Ronald A. Warren