Abstract: A method and system for address translation mapping of logical partitions for address translation buffer entries in a data processing system is provided. The method comprises receiving a logical address for a memory reference to a selected logical partition of a plurality of logical partitions of a particular block of virtual memory, wherein the block of virtual memory is divided into the plurality of logical partitions, and wherein the logical address includes a plurality of logical partition selection bits selecting the selected logical partition from among the plurality of logical partitions.

Abstract: A dynamic address translation mechanism uses a single translation look aside buffer (TLB) facility for pages of various sizes. The single TLB is supported by a small amount of special hardware. This hardware includes logic for detecting a page size prior to translation and generating a mask. The logic selects a set of virtual address bits for addressing the entries in the TLB. Parts of the virtual address are masked and merged with the address read out of the TLB to form the real address.

Abstract: A technique and a mechanism accurately determines the correct prefetch line for loops with strides of 1, N, or a combination of stride values. Stride registers are used to assist in prefetching. Furthermore, stride register values can be used to specify "cacheability" of data on an object by object basis to prevent "cache flushing". The compiler uses a new instruction, "MOVE GPR TO STRIDE REGISTER", prior to a loop to insert the "calculated stride value(s)" into the stride register(s) associated with the index register(s) which will be incremented by that stride value. At the end of the loop, a second new instruction, "CLEAR STRIDE REGISTER SET", is used to place a value of zero in all of the stride registers to inhibit prefetching of data which would most likely not be used. A zero value in the stride registers inhibits prefetching. Non-zero values in the stride registers clearly mark the execution of a loop, which is where prefetching makes the most sense.

Abstract: A dental handpiece sterilizer includes a sterilization chamber with an internal manifold system having outlet connectors into which dental handpieces can be plugged. A sterilant vapor introduced to the manifold flows through the dental handpieces coupled to the manifold and into the interior of the chamber so that it contacts the exterior surfaces of the handpieces before exiting the sterilant chamber.

Abstract: A queue structure is functionally equivalent to individual FIFO bank queues but requires only slightly more hardware than the single BSM queue approach. The queue structure uses "self-advancing" WAITING queues (one per BSM) in which there is a one-to-one correspondence between a (valid) queue position and a busy bank within a given BSM. However, the position/bank relationship is dynamically managed such that positions only exist for busy banks, thereby essentially providing a FIFO queue per bank while maintaining one queue per BSM.

Abstract: A memory system for a high performance data processing system comprises a plurality of memory modules. In the preferred embodiment, there are 2.sup.N +1 memory modules. In a specific example, there are 65 such modules. When all 65 modules are enabled, a real-to-physical translation unit generates logical module addresses from 0 to 64 using modulo 65 calculations. Once a module failure is detected, the translation unit maps the real addresses to logical module addresses from 0 to 63 by performing modulo 64 calculations. The contiguous set of logical module addresses are then mapped to a set of physical module addresses which do not include the failed module.

Abstract: A dynamic address translation mechanism includes a first directory-look-aside-table (DLAT) for 4KB page sizes and a second DLAT for 1MB page sizes. The page size does need not be known prior to DLAT presentation. When a virtual address is presented for translation, it is applied simultaneously to both DLATs for translation by either DLAT if it contains a page address entry corresponding to the virtual address presented. If a DLAT "miss" occurs, segment/page table searching is initiated. The DLAT page sizes are preferably made equal to the segment/page sizes and placed on 4KB and 1MB boundaries. Virtual page addresses lie within either a 1MB page or a 4KB page, and an entry for any virtual address can exist in only one (not both) of the DLATs.