Patents by Inventor Steven Waldstein

Steven Waldstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Physical layers
    Publication number: 20070007995
    Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.
    Type: Application
    Filed: August 14, 2006
    Publication date: January 11, 2007
    Inventors: Steven Waldstein, Maurice Richard, Alexander Alexeyev, David Reynolds
  • Physical layers
    Publication number: 20050024089
    Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.
    Type: Application
    Filed: January 16, 2004
    Publication date: February 3, 2005
    Inventors: Steven Waldstein, Maurice Richard, Alexander Alexeyev, David Reynolds