Patents by Inventor Steven Wallach

Steven Wallach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data processing system having a unique address translation unit
    Patent number: 4532590
    Abstract: A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege.
    Type: Grant
    Filed: December 21, 1982
    Date of Patent: July 30, 1985
    Assignee: Data General Corporation
    Inventors: Steven Wallach, Kenneth D. Holberger, Steven M. Staudaner, Carl Henry
  • Data processing system having instruction responsive apparatus for both a basic and an extended instruction set
    Patent number: 4434459
    Abstract: A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded.
    Type: Grant
    Filed: April 25, 1980
    Date of Patent: February 28, 1984
    Assignee: Data General Corporation
    Inventors: Charles J. Holland, Steven Wallach, Carl J. Alsing
  • Hierarchial memory ring protection system using comparisons of requested and previously accessed addresses
    Patent number: 4409655
    Abstract: A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses. The system uses hierarchical memory storage using in a particular embodiment eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The segment locations are designated by successive segment numbers having a descending order of protection with reference to data accesses thereto. A current address for data access includes a segment identification and a comparison is made with the segment identification of a preceding address to determine whether access can be made by the current address.
    Type: Grant
    Filed: April 25, 1980
    Date of Patent: October 11, 1983
    Assignee: Data General Corporation
    Inventors: Steven Wallach, Kenneth D. Holberger, David L. Keating, Steven M. Staudaher
  • Data processing system
    Patent number: 4386399
    Abstract: A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege.
    Type: Grant
    Filed: April 25, 1980
    Date of Patent: May 31, 1983
    Assignee: Data General Corporation
    Inventors: Edward Rasala, Steven Wallach, Carl J. Alsing, Kenneth D. Holberger, Charles J. Holland, Thomas West, James M. Guyer, Richard W. Coyle, Michael L. Ziegler, Michael B. Druke