Abstract: An AESA antenna configuration for simultaneous transmission and receiving of communication signal includes: a housing having eight sides; four transmit sides and four receive sides alternating there between and forming a 45 degree angle with their respective neighbor sides, where cross sections of the housing in a plane perpendicular to a vertical axis of the housing are tapered from a top to a bottom of the housing in the vertical direction by a cant angle.

Abstract: An AESA antenna configuration for simultaneous transmission and receiving of communication signal includes: a housing having eight sides; four transmit sides and four receive sides alternating there between and forming a 45 degree angle with their respective neighbor sides, where cross sections of the housing in a plane perpendicular to a vertical axis of the housing are tapered from a top to a bottom of the housing in the vertical direction by a cant angle.

Abstract: A baseband shaping device includes a plurality of coefficient memories, each memory having an input address bus, a multiplexor input and a coefficient value output. The device further includes a plurality shift registers, each having an input coupled to a respective one of the coefficient value outputs, a digital to analog clock input and an output. The device further includes a plurality of negative value circuits, each circuit having an input coupled to a respective one of the first shift register outputs and an output, a plurality of multiplexors, each having a first input coupled to a respective one of the first shift register outputs and a second input coupled to a respective one of the output of the plurality of negative value circuits. The device further includes a plurality of second shift registers, and an adder having a plurality of inputs coupled to the plurality of second shift registers.

Abstract: A baseband shaping device includes a plurality of coefficient memories, each memory having an input address bus, a multiplexor input and a coefficient value output. The device further includes a plurality shift registers, each having an input coupled to a respective one of the coefficient value outputs, a digital to analog clock input and an output. The device further includes a plurality of negative value circuits, each circuit having an input coupled to a respective one of the first shift register outputs and an output, a plurality of multiplexors, each having a first input coupled to a respective one of the first shift register outputs and a second input coupled to a respective one of the output of the plurality of negative value circuits. The device further includes a plurality of second shift registers, and an adder having a plurality of inputs coupled to the plurality of second shift registers.