Abstract: The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.

Abstract: Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein the shared cache memory is effectively shared on a line-by-line basis among the plurality of logical processing partitions of the multi-core processor.

Abstract: Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

Abstract: Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

Abstract: Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

Abstract: Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favors longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.

Abstract: Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

Abstract: A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining static and dynamic characteristics for the instructions; selecting a modification factor for the instructions based on a number of separate equivalent sections forming a cache in a processor which is processing the instructions; and modifying the instructions to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.

Abstract: Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favours longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.

Abstract: A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse analysis, and performs loop transformations, such as node splitting, loop distribution or stream unrolling to get the proper number of streams. Static prediction and run-time profile information are used to guide loop and stream selection. Compile-time loop cost analysis and run-time check code and versioning are used to determine the number of cache lines ahead of each reference for data cache line zeroing and to tolerate required data alignment relative to data cache lines.

Abstract: In a processor, when a conditional branch instruction is encountered, a software prediction for the conditional branch is made as a function of the specific condition register field used to store the branch condition for the conditional branch instruction. If a specified condition register field is not used, the software prediction may be made dependent upon the specific address at which the branch instruction is located.

Abstract: The mechanism to reduce instruction cache miss penalties by initiating an early cache line prefetch is implemented. The mechanism provides for an early prefetch of a next succeeding cache line before an instruction cache miss is detected during a fetch which causes an instruction cache miss. The prefetch is initiated when it is guaranteed that instructions in the subsequent cache line will be referenced. This occurs when the current instruction is either a non-branch instruction, so instructions will execute sequentially, or if the current instruction is a branch instruction, but the branch forward is sufficiently short. If the current instruction is a branch, but the branch forward is to the next sequential cache line, a prefetch of the next sequential cache line may be performed. In this way, cache miss latencies may be reduced without generating cache pollution due to the prefetch of cache lines which are subsequently unreferenced.

Abstract: A processor (100) includes a preload queue (160) for storing a plurality of preload entries. Each preload entry is associated with a preload instruction and includes the address and byte count defined by the respective preload and an identifier associated with the respective preload. A comparison unit (170) associated with the preload queue (160) identifies each conflicting preload entry, that is, each preload entry associated with a preload instruction that conflicts with an older store instruction. The oldest preload instruction associated with one of the conflicting preload entries represents a target preload. The processor (100) may flush this target preload along with all instructions executed after the target preload in order to correct for the conflict between the target preload and store instruction.

Abstract: A mechanism and method for a store data queue are implemented. Address translation operations for store instructions in a data processor are decoupled from data operations by initiating address translation before source data operands are available. A store data queue snoops the finish buses of execution units for the source operand. A data entry in the data queue that is allocated at dispatch of the store instruction snoops for the source operand required by its corresponding instruction. The data operand is then communicated to a memory device in instruction order thereby simplifying the detection of conflicting stores.

Abstract: In maintaining the state of a processor, a dispatched instruction is given an identification tag and an associated entry in an architectural register table. The identification tag of the dispatched instruction is written to the entry in the architectural register table, if the identification tag of the dispatched instruction is more recent than a prior instruction identification tag stored in the entry.

Abstract: A method and system in a data processing system for accessing information using an instruction specifying a memory address is disclosed. The method and system comprises issuing the instruction to an execution unit and storing an address derived from the specified address. The method and system also includes accessing a cache to obtain the information, using the derived address and determining, in response to a signal indicating that there has been a cache miss, if there is a location available to store the specified address in a queue. According to the system and method disclosed herein, the present invention allows for dynamic pipeline expansion of a processor without splitting this function between components depending upon the reason expansion was required, thereby increasing overall system performance.

Abstract: One aspect of the invention relates to a super scalar processor having a memory which as addressable with respect to the combination of a page address and a page offset address, and provides a method for detecting an overlap condition between a present instruction and a previously executed instruction, the previously executed instruction being executed prior to execution of the present instruction. In one embodiment, the method comprises the steps of dividing the present instruction into a plurality of aligned memory accesses; determining the page offset for at least one of the aligned accesses; and comparing the page offset and byte count for the present instruction to a page offset and byte count for the previously executed instruction.

Abstract: In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.

Abstract: An apparatus and method for processing multiple cache misses to a single cache line in an information handling system which includes a miss queue for storing requests for data not located in a level one cache and a comparator for comparing requests for data stored in the miss queue to determine if there are multiple requests for data located in the same cache line of a level two cache. Each new request for data from the same cache line of the level two cache as an older original request for data in the miss queue is marked as a load hit reload. The requests marked as load hit reloads are then grouped together with the matching original request and forwarded together to the level two cache wherein the original request requests the data from level two cache. The load hit reload requests do not access level two cache but instead bypass access of level two cache by extracting data from the cache line outputted from level two cache for the matching original request.

Abstract: To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed prior to a logically prior store instruction, and where the load instruction received data for the location prior to being modified by the store instruction, and the correct data for the load instruction included bytes from the store instruction. Additionally, to execute store instructions out-of-order with respect to load instructions, a mechanism is implemented to keep a store instruction from destroying data that will be used by a logically earlier load instruction. Further, to support load instructions that are executed out-of-order with respect to each other, a mechanism is implemented to insure that any pair of load instructions (which access at least one byte in common) return data consistent with executing the load instructions in order.