Abstract: A solid state memory disk that stores data on a sector basis is described. The solid state disk includes an array of FLASH memory devices, which store the sectors of data. Each block of memory within the FLASH array includes data space for storing many sectors of data and a block sector translation table. The block sector translation table identifies each sector of data stored in the block's data space by a sector number. The solid state disk also includes a controller. Among its many responsibilities, the controller manages the writing of sector data into the array and the reading of sectors of data from the array. The controller responds to a write request by seeking an earlier version of the sector which has a logical sector number equal to the sector's sector number and marking that sector dirty. Afterward, the controller allocates free memory space for the sector of data. The sector of data is then written into the allocated memory space.

Abstract: A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.

Abstract: A method of cleaning-up a solid state memory disk is described. Clean-up begins with the selection of a focus block for clean-up. Next, on a sector-by-sector basis, memory is allocated within a destination block to store valid sectors of user data. User data is then copied into the destination block on a sector-by-sector basis. Afterward, the focus block is erased, converting dirty sectors into free memory without loss of valid sectors of data.

Abstract: A solid state memory disk with increased reserve memory is described. The solid state memory disk includes an array of solid state memory devices for storing user data and reserve memory, which includes both free memory and dirty memory. The solid state memory disk also includes a controller, a clean-up state machine, and a data compressor. The data compressor increases reserve memory by compressing data received from a host and coupling compressed data to the array of memory devices under the control of the controller. In response to write commands from the host, the controller writes a first sector data, which has been compressed, to a first location in a first block within a memory device. Reserve memory within the array is thus increased, so long as the maximum number of sectors the host is allowed to write is less the average compression ratio of the data compressor multiplied by the capacity of the solid state disk. A method of increasing reserve memory in a solid state disk is also described.

Abstract: Apparatus for controlling a length of a period during which the output circuitry of a memory array waits before latching the output data including apparatus for detecting the presence of an error in data read from an memory array, apparatus for providing a first value to determine a wait period, apparatus responsive to the detection of an error for providing a second value, apparatus responsive to the first value for generating a signal to latch a data output from the memory array after a first period and responsive to the second value for generating a signal to latch a data output from the memory array after a second period.

Abstract: A method of allocating free physical memory in a solid state memory disk for a sector of data of a given size is described. Allocation begins by determining whether sufficient free memory remains in the block to which the previous sector of data was written. If there is not sufficient free memory remaining, then selection of another block to allocate the sector of data begins. The selection is based on the sum of the amount of free memory in a selected block and one of the following: 1) the amount of invalid data in the block; 2) the cycle count for the block; 3) the amount of invalid data as compared to a maximum amount of invalid data for all non-volatile memory devices associated with the block; and 4) the number of blocks already allocated to all non-volatile memory devices associated with the block. Afterward, the block with the greatest amount of available memory is selected to store the sector of data.

Abstract: A method for storing data in a generally-diagonal pattern in blocks of a flash EEPROM array by which the least number of memory cells are affected by a failure of either a row conductor or a column conductor, and apparatus for addressing the flash array to produce such a generally-diagonal storage pattern. The arrangement allows the simplest forms of error detection and correction circuitry to be utilized.

Abstract: A method of initiating and controlling background clean-up of a solid state memory disk is described. Background clean-up begins by enabling a clean-up state machine after completion of a write command. Next, a next state pointer is set to an initial state for evaluating whether clean-up is necessary. Actual execution of background clean-up begins when the processing unit allocates execution time for clean-up. As each state is executed, the next state pointer is reset so that it points to the next clean-up state to be executed. States pointed to by the next state pointer are executed until a block of the solid state memory disk is cleaned-up.Also described is a method of automatically performing foreground clean-up of a solid state memory disk. A method of forcing clean-up is also described.

Abstract: A method of utilizing circuitry including error detecting and correcting circuitry to detect and correct errors which can occur in data stored in multi-bit per cell format in a flash EEPROM memory array before those errors can affect the accuracy of data provided by a flash EEPROM memory array.

Abstract: Apparatus for controlling a length of a period during which the output circuitry of a memory array waits before latching the output data including apparatus for detecting the presence of an error in data read from an memory array, apparatus for providing a first value to determine a wait period, apparatus responsive to the detection of an error for providing a second value, apparatus responsive to the first value for generating a signal to latch a data output from the memory array after a first period and responsive to the second value for generating a signal to latch a data output from the memory array after a second period.

Abstract: A method of detecting the loss of a sector of data stored in a solid state memory disk is described. Detection is enabled by the creation of a header for each sector number during formatting. Each header includes a logical sector number equal to a sector number. Location and loss of a sector of data associated with a particular sector number is aided by a sector header translation table. The sector header translation table stores an offset, or pointer, for each sector number that points to its associated header. The method by which the sector header translation table is generated aids in the detection of lost sectors of data. Upon power-up, each offset in the sector header translation table is initialized to an initial, invalid value. Afterward, the nonvolatile semiconductor memory is scanned and the sector header translation table is modified so that for each sector number it points to the header including a logical sector number equal to the sector number.

Abstract: A method is described for locating content addressable memory (CAM) bit cells on a column within a main memory array and within the guard ring surrounding the main memory array.

Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port controller for receiving command instructions from a data bus coupled to the memory device. Instruction words to a command port controller operates to instruct the device to perform read, erase, program, or verify functions and the command port controller generates necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.

Abstract: A mortar applying device (10) includes a motor (12) and hopper (14) mounted on a wheeled (18 and 50) frame (32). The wheels (18) can be driven at variable speeds using the throttle of the engine (12) to accommodate faster and slower rates of block laying. At the forward end of the frame (32) is an arm (34) and wheel (36) assembly which senses the end of the wall under construction and which activates motor cut off switch (44). The hopper (14) is lined with a low coefficient of friction, low adhesion material (70) to prevent mortar from clinging inside the hopper (14). The discharge element (66) located under the open bottom (64) of the hopper (14) includes an angled guide (72) which directs mortar out two exit ports (74 and 76). The height of the ribbons of mortar exiting under gates (80 and 82) is controllable and is smoothed over by a bevelled edge (88).

Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.