Abstract: A signal timing circuit for use in re-timing circuits in digital signal regenerators in long distance telecommunications systems is disclosed. A phase control circuit controls the timing of clock signal relative to digital signals at a re-timing gate by means of a negative feedback loop and a phase shifter. The feed back loop maintains the desired relative timing in dependence upon a reference voltage (V.sub.ref) and a voltage (V.sub.var) obtained from the phase difference of the input digital signals (.phi..sub.i) and the output digital signals (.phi..sub.o) of the re-timing gate.