Patents by Inventor Stewart Crozier
Stewart Crozier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10601449Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: September 18, 2019Date of Patent: March 24, 2020Assignee: INPHI CORPORATIONInventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Publication number: 20200014407Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: ApplicationFiled: September 18, 2019Publication date: January 9, 2020Applicant: INPHI CORPORATIONInventors: Benjamin SMITH, Arash FARHOODFAR, Stewart CROZIER, Frank R. KSCHISCHANG, Andrew HUNT
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Patent number: 10461781Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: June 18, 2018Date of Patent: October 29, 2019Assignee: INPHI CORPORATIONInventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Publication number: 20180302108Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: ApplicationFiled: June 18, 2018Publication date: October 18, 2018Inventors: Benjamin SMITH, Arash FARHOODFAR, Stewart CROZIER, Frank R. KSCHISCHANG, Andrew HUNT
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Patent number: 10033410Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: July 8, 2016Date of Patent: July 24, 2018Assignee: INPHI CORPORATIONInventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Publication number: 20160322989Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: ApplicationFiled: July 8, 2016Publication date: November 3, 2016Inventors: Benjamin SMITH, Arash FARHOODFAR, Stewart CROZIER, Frank R. KSCHISCHANG, Andrew HUNT
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Patent number: 9413493Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: June 18, 2015Date of Patent: August 9, 2016Assignee: Cortina Systems, Inc.Inventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Publication number: 20150288485Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Patent number: 9083492Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: February 13, 2014Date of Patent: July 14, 2015Assignee: Cortina Systems, Inc.Inventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Publication number: 20140233673Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 400/1000 communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: ApplicationFiled: February 13, 2014Publication date: August 21, 2014Applicant: CORTINA SYSTEMS, INC.Inventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Patent number: 8352840Abstract: The invention relates to improving the performance of sequence-based soft-output decoders using event cleanup processing, wherein combinations of potential error events are evaluated using an error detection code (EDC) to select events that produce a modified set of decisions that has no EDC detectable errors. The event cleanup method and associated event cleanup decoder enable to significantly improve the error rate performance of sequence-based decoders and/or significantly improve decoding efficiency compared to other known error cleanup methods.Type: GrantFiled: March 25, 2009Date of Patent: January 8, 2013Assignee: Her Majesty The Queen in Right of Canada, As Represented by The Minister of Industry, Through The Commincations Research Centre CanadaInventors: Stewart Crozier, Kenneth Gracie
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Publication number: 20090249165Abstract: The invention relates to improving the performance of sequence-based soft-output decoders using event cleanup processing, wherein combinations of potential error events are evaluated using an error detection code (EDC) to select events that produce a modified set of decisions that has no EDC detectable errors. The event cleanup method and associated event cleanup decoder enable to significantly improve the error rate performance of sequence-based decoders and/or significantly improve decoding efficiency compared to other known error cleanup methods.Type: ApplicationFiled: March 25, 2009Publication date: October 1, 2009Applicants: the Communications Research Centre CanadaInventors: Kenneth Gracie, Stewart Crozier
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Patent number: 6145114Abstract: The invention comprises an enhancement to max-log-APP processing that significantly reduces performance degradation associated with introducing the "max" approximation into log-APP computations, while still maintaining lower computational complexity associated with max-log-APP processing. This enhancement is achieved by adjusting extrinsic information produced by a max-log-APP process where the magnitude of the extrinsic information is reduced, for example, by multiplying it with a scale factor between 0 and 1.Type: GrantFiled: August 14, 1998Date of Patent: November 7, 2000Assignee: Her Majesty the Queen in right of Canada, as represented by the Minister of Industry through Communications Research CentreInventors: Stewart Crozier, Andrew Hunt, John Lodge
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Patent number: 6145111Abstract: A method of encoding data is described herein. According to the method, source data elements are coded using one or more product codes having a common component code. The resulting one or more primary product codewords consist of a plurality of first codewords of the common component code. One or more first sets of codewords of the common component code are assembled such that each of the first sets comprises two or more distinct first codewords forming part of a same primary product codeword. Each of the codewords of each of the first sets is codeword-mapped to a second codeword of the common component code using a one-to-one codeword-mapping. One or more second sets of second codewords are provided, where each second set corresponds to a first set of codewords. The codeword-mapping includes re-ordering, according to a known interleaving pattern, the symbols within a codeword.Type: GrantFiled: August 14, 1998Date of Patent: November 7, 2000Assignee: Her Majesty the Queen in right of Canada, as represented by the Minister of Industry through Communications Research CentreInventors: Stewart Crozier, Andrew Hunt, John Lodge