Abstract: Data processing apparatus is described, comprising an array of data processing elements in rows and columns. Each element has a data register for input/output. Each column of data registers can be interconnected to form a serial shift path containing either (a) the even-numbered registers, (b) the odd-numbered registers or (c) all the registers. This allows data to be shifted out of the array, one row at a time, either from the even rows, the odd rows, or all the rows. Data can be shifted into the array in a similar way. The facility for selecting the even or odd rows is useful for handling interlaced image data.

Abstract: An array processor consisting of integrated circuit chips connected in a rectangular array. The number of terminals on each chip necessary for these interconnections is reduced by arranging for certain terminals to be connected to branched paths, so that those terminals are shared between different connections. Special gating is provided to ensure that signals are routed correctly over these shared connections.

Abstract: An array processor is described consisting of a plurality of modules connected together in rows and columns. Each module has at least one special terminal which, as well as providing a connection for transfer of data between adjacent modules, also provides an output which is combined with similar signals from the other modules in the same row, to form a row response signal. Alternate modules in each row are rotated by 180.degree. with respect to each other, so that the special terminals on adjacent modules are connected in pairs. This reduces the complexity of the circuits for forming the row response signals.