Abstract: Temperature monitoring systems for data centers include a plurality of ceiling-mounted infrared sensor arrays. Each infrared sensor array includes a two-dimensional array of infrared emission sensors, and at least some of the infrared emission sensors have field of view patterns that project onto aisle faces of equipment racks that are mounted in rows in the data center. These systems may further include a controller that is remote from at least some of the infrared sensor arrays and that is in communications with the infrared sensor arrays, the controller configured to provide a two-dimensional thermal map of the aisle faces of the equipment racks based at least in part on temperature data received from the infrared sensor arrays.

Abstract: Temperature monitoring systems for data centers include a plurality of ceiling-mounted infrared sensor arrays. Each infrared sensor array includes a two-dimensional array of infrared emission sensors, and at least some of the infrared emission sensors have field of view patterns that project onto aisle faces of equipment racks that are mounted in rows in the data center. These systems may further include a controller that is remote from at least some of the infrared sensor arrays and that is in communications with the infrared sensor arrays, the controller configured to provide a two-dimensional thermal map of the aisle faces of the equipment racks based at least in part on temperature data received from the infrared sensor arrays.

Abstract: Hoteling systems for open work areas are provided that may be used track occupancy of work spaces within the work area. These systems include a plurality of infrared sensor arrays that are mounted above the work area. Each infrared sensor array includes a two-dimensional array of infrared emission sensors. The field of view patterns of at least some of the infrared emission sensors project into the work spaces. These systems further include a controller that is remote from at least some of the infrared sensor arrays. The controller is configured to determine an occupancy state of each of the work spaces based at least in part on information received from the infrared sensor arrays.

Abstract: The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.

Abstract: A technique for allocating stack bus bandwidth based on the offered load of each stack member coupled to the stacking bus allocates access opportunities to the stack bus based on the ratio of the offered loads of the coupled stack members.

Abstract: A ring access system, for use in system having a plurality of routing platforms coupled by redundant rings, that allows access to either ring when a token is received at a first ring if all outstanding locally-sourced data has been stripped from the second ring.

Abstract: A cross stack port aggregation method and system associates a destination index with a received packet when it is provided to devices in the stack. Each device utilizes the destination index to access a descriptor identifying ports in the device included in the port aggregation group. An index generated from packet address data is used to select a bit in a group mask unique to each port.

Abstract: A 10/100Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin) represents a reduction in the number of pins associated with each port and is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional 100Base-T interface specified by IEEE 802.3u (clause 22). As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on sixteen wires in a conventional 100Base-T interface at 25 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 125 MHz, five times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis.

Abstract: Provided is a 10/100Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional 100Base-T interface specified by IEEE 802.3u (clause 22). As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on sixteen wires in a conventional 100Base-T interface at 25 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 125 MHz, five times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis.

Abstract: An SFP module provides either a 1000Base-X or SGMII interface protocol to a host and provides a 1000Base-T media dependent interface (MDI). If the SFP module is coupled a host that only implements the 1000Base-X protocol then the SFP module translates the 1000Base-X protocol to the 1000Base-T protocol so that the host MAC sees the 1000Base-T SFP module as if it were an optical transceiver. If the host implements SGMII then the SFP performs auto-negotiation of speed and communicates with the host implement data transfer at a selected rate, e.g., 10, 100, or 1000 Mbps.

Abstract: A system and method are disclosed for providing a method of communicating between a media access control (MAC) layer and a physical (PHY) layer. The method includes sending a 100 MHz time-division multiplexed signal on a receive data line and sending a time-division multiplexed receive control signal on a receive control line. A 100 MHz time-division multiplexed signal is sent on a transmit data line and a time-division multiplexed transmit control signal is sent on a transmit control line.

Abstract: An SFP module provides either a 1000Base-X or SGMII interface protocol to a host and provides a 1000Base-T media dependent interface (MDI). If the SFP module is coupled a host that only implements the 1000Base-X protocol then the SFP module translates the 1000Base-X protocol to the 1000Base-T protocol so that the host MAC sees the 1000Base-T SFP module as if it were an optical transceiver. If the host implements SGMII then the SFP performs auto-negotiation of speed and communicates with the host implement data transfer at a selected rate, e.g., 10, 100, or 1000 Mbps.

Abstract: The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.

Abstract: Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.

Abstract: Provided is a 10Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional seven-wire interface. As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on nine wires in a conventional seven-wire interface at 10 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 40 MHz, four times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis.

Abstract: Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.

Abstract: Provided is a 10/100Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional 100Base-T interface specified by IEEE 802.3u (clause 22). As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on sixteen wires in a conventional 100Base-T interface at 25 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 125 MHz, five times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis.

Abstract: Provided is a 10/100Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional 100Base-T interface specified by IEEE 802.3u (clause 22). As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on sixteen wires in a conventional 100Base-T interface at 25 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 125 MHz, five times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis.

Abstract: A memory system reducing or eliminating the effects of DRAM page-opening delays or row access delays is provided. The system uses DRAM and fast memory such as SRAM. SRAM is used to store the initial portions of data from data blocks and corresponding portions of DRAM are used to store the terminal portions of data from the data blocks. When access to a block of data is requested, DRAM row access procedures are initiated. During the delay period, while DRAM row access procedures are occurring, the initial portion of data from the requested block is read-out from SRAM. By about the time the initial data read-out from SRAM is completed, DRAM row access procedures are completed and the remaining portion of the data is read-out from DRAM.

Abstract: Provided is a 10Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional seven-wire interface. As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on nine wires in a conventional seven-wire interface at 10 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 40 MHz, four times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis.