Patents by Inventor Stewart G. Kenly

Stewart G. Kenly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940827
    Abstract: An electronic control system provides selectable path operation, such as linear and pulse-width modulated (PWM) operation and provides path transition management to improve operation. The system supplies a current or a voltage to a load in response to an input signal or value and includes an output driver, and multiple selectable control paths. The system includes a control circuit that selects between the first control path and the second control path in response to a path selection indication to drive the output driver. The system may include an evaluator that determines the path selection indication in conformity with an amplitude and a slew rate of the input. One or all of the control paths may have a response time to changes in the input signal or value, and the control circuit may delay switching from the second control path to the first control path to compensate for the response time.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: March 26, 2024
    Inventors: Stewart G. Kenly, Vamsikrishna Parupalli, Nishant Jain, Eric B. Smith
  • Patent number: 6754171
    Abstract: Protection from a distributed clock failure in a packet switched network device involves monitoring primary clocking information that is received from an input port of the network device, distributing the clocking information to an output port for use in synchronous transmissions, and supplying backup clocking information from within the packet switched network device to the output port if the primary clocking information fails. In an embodiment, the integrity of the primary clocking information is directly monitored in hardware and the backup clocking information is provided by a local clock source that is located within the network device. If a failure in the primary clocking information is detected, the backup clocking information is supplied to the output port from the local clock source.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: June 22, 2004
    Assignee: Enterasys Networks, Inc.
    Inventors: Daniel J. Bernier, Deborah E. Edin, Stewart G. Kenly