Abstract: A non-volatile memory cell structure comprises a floating gate, a reverse breakdown injection element at least partially formed in a polysilicon layer and operatively coupled to the floating gate, and a transistor at least partially formed in a region of a semiconductor substrate, operatively coupled to the floating gate. In a further aspect, a control gate is capacitively coupled to the floating gate and is formed in said polysilicon layer. The reverse breakdown electron injection element comprises a first, second, and third active regions, the first and second regions comprising a first p/n junction, the second and third active regions comprising a second p/n junction.

Abstract: A non-volatile memory cell structure which includes a floating gate, a reverse breakdown element and a read transistor. The reverse breakdown element is at least partially formed in a first region of a first conductivity type in a semiconductor substrate, and underlies a portion of the floating gate; and the read transistor is at least partially formed in the first region and connected to the reverse breakdown element. In a further embodiment a control gate is capacitively coupled to the floating gate and is formed in a second region of the substrate, outside the well region.

Abstract: A method of creating a reverse breakdown condition in an array of memory cells arranged in columns and rows in the array, and an array structure are provided. The method comprises the steps of applying a first voltage on a first column connection coupling a first column of said cells, and a second voltage on a second column connection coupling a second column of said cells; and applying a third voltage on a first row connection coupling a first row of said cells, and applying said second voltage on a second row connection coupling a second row of said cells. In this aspect, the difference between the first voltage and the third voltage creates said reverse breakdown condition in at least one cell occupying said first column and first row. In a further aspect, each cell includes a floating gate and the method of the invention includes the step of programming one of said cells by coupling a control voltage to each floating gate.

Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.

Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.