Patents by Inventor Stewart Griffin Hall

Stewart Griffin Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Emulation of fused multiply-add operations
    Patent number: 9645792
    Abstract: At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: May 9, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Pramod Vasant Argade, Andrew Evan Gruber, Chiente Ho, Stewart Griffin Hall, Lin Chen
  • EMULATION OF FUSED MULTIPLY-ADD OPERATIONS
    Publication number: 20160048374
    Abstract: At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.
    Type: Application
    Filed: August 18, 2014
    Publication date: February 18, 2016
    Inventors: Pramod Vasant Argade, Andrew Evan Gruber, Chiente Ho, Stewart Griffin Hall, Lin Chen