Abstract: The present invention is an approach for verifying the operation of read only memory digital pads associated with the switching network digital switching system. Any failures are detected and an indication is transmitted for fault detection and recovery.

Abstract: An arrangement for interfacing the originating time stage (OTS) and terminating time stage (TTS) of a time and control unit (TCU) to the space stage of T-S-T digital switching system. The space stage includes an intra-path through the space stage as well as an interpath. The interface transmits PCM samples simultaneously from the OTS to both the intra and interpaths of the space stage. PCM samples from the space stage are received by an intra buffer and an inter buffer from the intra path and inter path respectively. A TCU control memory gates and connects either the intra buffer or inter buffer to the TTS.

Abstract: A space stage for a T-S-T digital switching system is shown arranged into modular functional elements. The elements are combined allowing the space stage to grow modularly to interconnect from one to thirty-two originating time stages and terminating time stages.

Abstract: A space stage for a T-S-T digital switching system is shown arranged into four identical space stage units (SSU). Each SSU is arranged into modular functional elements. The elements are combined in each SSU to allow the space stage to grow modularly, interconnecting from thirty-two to sixty-four originating time and terminating time stages.

Abstract: A space stage for a T-S-T digital switching system is shown arranged to interconnect the originating time stages (OTS) and terminating time stages (TTS) of a first time group and the OTS's and TTS's of a second time group. The space stage includes four identical space stage units (SSU). The first SSU interconnects the OTS's and TTS's of the first time group and the second SSU the OTS's and TTS's of the second time group. The third SSU interconnects the OTS's of the first time group to the TTS's of the second time group and the fourth SSU interconnects the OTS's of the second time group to the TTS's of the first time group.

Abstract: An arrangement for the distribution of digital service tones in a distributed processor digital switching network is shown. These service tones are distributed between the time stages of the digital switching network with a minimum of interprocessor communication. This is accomplished by transmitting the particular service tone, from the terminating time stage which detects the need for tone application, through the switching network paths already established for voice communication. These service tones include such tones as reorder tone, dial tone, busy tone, DTMF tones, MF tones and ringback tone.

Abstract: This fault recovery system determines the integrity of a duplex digital PCM switching network. The two copies of the switching network operate in synchronization and comparison of the outputs of each copy of the switching network takes place in order to detect network faults. The fault recovery mechanism is chiefly provided by inserting PCM samples from maintenance registers into the PCM data stream, through the digital switching network and trapping said PCM sample for analysis by the program. Subsequently, the logical unit corresponding to each fault is determined and a count is recorded corresponding to each unit.