Abstract: A device for obtaining a jitterstable synchronization of a counter which has a clock input for receiving bit timing pulses from a remote control unit, an output for supplying regenerated frame timing pulses, and a reset input comprises: a phase comparator means which has an output arranged to supply an output signal if, and only if, a lag of the leading edge or a lead of the trailing edge occurs for the regenerated frame timing pulses transmitted from the counter relative to frame timing pulses transmitted from the control unit; and a memory means which has a signal input connected to the output of the phase comparator means, a clock input for receiving the bit timing pulses and reacting to an edge opposite to the edge on which the clock input of the counter is arranged to react, and an output connected to the reset input of the counter to reset the latter in dependence on whether the output signal from the phase comparator means is supplied.