Patents by Inventor Stig Oresjo

Stig Oresjo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for confirming electrical connection defects
    Patent number: 6853744
    Abstract: An improved circuit board inspection system incorporates a technique that confirms observed electrical connection defects. The improved circuit board inspection system applies a localized investigative routine upon portions of a printed circuit board having one or more identified defects. The technique accounts for the slope of a portion under test of the printed circuit board and provides results that are more accurate from inspection systems that report electrical connection defects.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: February 8, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Horst Mueller, Sunit Bhalla, Kris Kanack, Stig Oresjo
  • System and method for confirming electrical connection defects
    Publication number: 20030113009
    Abstract: An improved circuit board inspection system incorporates a technique that confirms observed electrical connection defects. The improved circuit board inspection system applies a localized investigative routine upon portions of a printed circuit board having one or more identified defects. The technique accounts for the slope of a portion under test of the printed circuit board and provides results that are more accurate from inspection systems that report electrical connection defects.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 19, 2003
    Inventors: Horst Mueller, Sunit Bhalla, Kris Kanack, Stig Oresjo
  • System for efficient utilization of multiple test systems
    Patent number: 6311301
    Abstract: A system for efficient utilization of multiple test systems may include an apparatus for testing an electronic circuit board, which comprises a number of computer readable media containing computer readable program code comprising code for a test analysis system that interfaces with at least two test systems. The test analysis system reads a description of said board's board topology and analyzes a number of potential defects of said board based on that description. The test analysis system creates at least two test procedures for the at least two test systems by creating a first test procedure to test the electronic circuit board on a first test system of the at least two test systems. The system then creates at least one other test procedure to test the electronic circuit board on at least one other test system of the at least two test systems.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: October 30, 2001
    Inventors: Kenneth E. Posse, Stig Oresjo, Patricia Monterio, Anne Dudfield
  • Post-mission test method for checking the integrity of a boundary scan test
    Patent number: 6243843
    Abstract: The invention is a method for assuring the integrity of a mission test. The method includes the steps of checking the integrity of the test after test execution but prior to test diagnosis. In particular, after the mission test has been executed, the integrity of the mission test is confirmed based on a comparison of the actual length of the scan path with an expected length of the scan path.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: June 5, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P. Parker, Stig Oresjo