Abstract: Broadly speaking, a method and apparatus is provided for identifying and responding to a deadlock condition in a SAS/SATA communication process. More specifically, an initiator device involved in the SAS/SATA communication process is defined to recognize a received error signal as an indication of a potential communication deadlock condition. The initiator device is further defined to promptly respond to the received error signal with a course of action for recovering from the communication deadlock condition.

Abstract: A method for utilizing a multi-channel SCSI chip capable of controlling different types of devices is disclosed. A first channel control is set and a second channel control is set in the SCSI chip. A first peripheral device type is managed using the first channel control and a second peripheral device type is managed using the second channel control.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus. In response to the active signal on the address increment disable line, the bus master inhibits changing the address for the duration of the data transfer. The module also drives an active signal on an expansion address off boundary line in the control bus when an internal expansion address of the module is not aligned with a natural boundary of a data bus of the internal communication bus to allow the bus master to adjust the width of the data transfer.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when additional time is needed to participate in the data transfer. If either the source module, destination module or both modules require more time, the bus master, in response to an active stretch bus access signal or signals for the module or modules, automatically extends the bus access cycle until all modules requiring additional time signal over the internal communication bus that they are ready to proceed with the data transfer. Consequently, the source module, destination module, or both modules can re-time a bus access cycle to accommodate the characteristics of that particular module. When the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus.

Abstract: A non-invasive processor bus master back off enables bus mastership to be changed without interrupting execution of time critical routines of the current bus master. The current bus master recognizes when a time critical routine is being executed. Thus, if a request to back-off the bus is received while a time critical routine is being executed, the current bus master completes execution of the time critical routine prior to pausing and relinquishing the bus to the requesting bus master. Non-invasive back-off structure includes a bus; a first bus master coupled to the bus where the first bus master executes routines that transfer data over the bus; a second bus master coupled to the bus; and a non-invasive back-off circuit coupled to the first and second bus masters.