Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed<=V2 and b) Vhigh?Vmed<=V1. If the drive circuit is a high side driver, the intermediate voltage node receives an intermediate voltage Vmed set below the high supply voltage and that mees the following conditions: a) Vmed<=V1 and b) Vhigh?Vmed<=V2. The circuit may be configured as a push pull driver by coupling a high side driver and low side driver in series.

Abstract: A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal.

Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.