Abstract: A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package.

Abstract: A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal.

Abstract: A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.

Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed<=V2 and b) Vhigh?Vmed<=V1. If the drive circuit is a high side driver, the intermediate voltage node receives an intermediate voltage Vmed set below the high supply voltage and that mees the following conditions: a) Vmed<=V1 and b) Vhigh?Vmed<=V2. The circuit may be configured as a push pull driver by coupling a high side driver and low side driver in series.

Abstract: A semiconductor integrated device is provided with: a die having a body of semiconductor material with a front surface, and an active area arranged at the front surface; and a package having a support element carrying the die at a back surface of the body, and a coating material covering the die. The body includes a mechanical decoupling region, which mechanically decouples the active area from mechanical stresses induced by the package; the mechanical decoupling region is a trench arrangement within the body, which releases the active area from an external frame of the body, designed to absorb the mechanical stresses induced by the package.

Abstract: A clamping circuit for a class AB amplifier includes a reference voltage circuit, four NPN Darlington transistors having inputs coupled to the reference voltage circuit, and outputs for providing four clamped voltages, and a split NPN Darlington transistor having an input coupled to the reference voltage circuit, and four separate outputs for providing four AC ground voltages.

Abstract: A bidirectional voltage differentiator circuit comprises start-up circuitry, sensing circuitry, and output circuitry coupled to logic circuitry. The start-up circuitry acts to start-up the sensing circuitry when the circuit is powered on, and accelerates the response of the sensing circuitry thereafter. The sensing circuitry senses variation in an input voltage applied to an input node. Responsive to the voltage variation sensed by the sensing circuitry, the output circuitry produces a state change at a first or second output node. The logic circuitry receives the states of the output nodes and produces a logic output signal to indicate the occurrence of the variation sensed in the input voltage. The voltage sensing circuit is operable to sense variation of the input voltage regardless of whether the voltage is rising or falling and without regard to the DC value of the input voltage.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract: A system comprises a resource, such as an interconnection, for example, of the Network-on-Chip (NoC) type, having an overall bandwidth available for allocation to a set of initiators that compete for allocation of the overall bandwidth. The system includes a communication arbiter for allocating the overall bandwidth to the initiators according to respective values of bandwidth requested (RBW) by the initiators. A control device (50) is configured to detect the deviation between the value of bandwidth allocated to the initiators and the respective value of requested bandwidth and allocate the overall bandwidth to the initiators in a dynamic way minimizing the mean value of the deviation.

Abstract: A method for designing a photolithography mask and a light source may include designing an initial photolithography mask and an initial light source using an initial target pattern corresponding to a desired target pattern in a resist layer. The method may also include designing a new target pattern and designing a new photolithography mask and/or a new light source using the new target pattern.

Abstract: An arrangement of at least two arithmetic logic units carries out an operation defined by a decoded instruction including at least one operand and more than one operation code. The operation codes and at least one operand are received and corresponding executions are performed by the arithmetic logic units on a single clock cycle. The result of the execution from one arithmetic logic unit is used as an operand by a further arithmetic logic unit. The decoding of the instruction is performed in an immediately preceding single clock cycle.

Abstract: The mass of an object may be estimated based on intersection points of a representation of a surface in an image space with cubes defining the image space, the surface representing a surface of an object. The representation may be, for example, based on marching cubes. The mass may be estimated by estimating a mass contribution of a first set of cubes contained entirely within the representation of the surface, estimating a mass contribution of a second set of cubes having intersection points with the representation of the surface, and summing the estimated mass contribution of the first set of cubes and the estimated mass contribution of the second set of cubes. The object may be segmented from other portions of an image prior to estimating the mass of the object.

Abstract: Image defects in digital images are easily detectable by the human eye but may be difficult to detect in a computer-implemented fashion. In an embodiment of a digital-image-acquisition device, defects are removed on the CFA domain before color interpolation takes place. In order to allow cancellation of couplets of defective pixels, a two pass embodiment is presented. Such embodiment presents methods and systems that can remove both couplets and singlets without damaging the image. The system includes a ring corrector that detects a defect in the ring of pixels that surround a central pixel, a singlet corrector that detects and corrects the central pixel and removes a couplet if the ring corrector is activated, whereas if the ring corrector is switched off, the singlet corrector only removes singlets, and a peak-and-valley detector that avoids overcorrection by avoiding correcting signal peaks or valleys in case of spikes or drops in signal.

Abstract: An image sensor having improved dynamic range includes a signal that is read out for a selection of pixels which act as a calibration to govern the choice of exposure levels to be applied to the rest of the array. In this way, the sensor is operable to adapt to variations in scene intensity. The pixels in the array are vertically and horizontally addressed so as to enable accounted for small areas of intensity variation across an imaged scene.

Abstract: A method may include a cycle of reading a current pixel including connecting the capacitive node of the pixel to a capacitive node of a previous pixel already read, connecting the capacitive node of the current pixel and the capacitive node of a previous pixel to an output line, reading a first voltage of the capacitive node of the pixel through the output line, transferring charges from the accumulation node to the capacitive node of the pixel, reading a second voltage of the capacitive node of the pixel through the output line, and disconnecting the capacitive node from the capacitive node of a previous pixel, and a cycle of reading a next pixel. This cycle may include accumulating charges in the accumulation node of the next pixel while the capacitive node of the current pixel is connected to a capacitive node of a previous pixel.

Abstract: An embodiment of a system for physical link adaptation in a wireless communication network such as e.g., a WLAN, selectively varies the physical mode of operation of the transmission channels serving the mobile stations in the network. The system includes an estimation module to evaluate transmission losses due to collisions as well as transmission losses due to channel errors over the transmission channel, and an adaptation module to select the physical mode of operation of the transmission channel as a function of the transmission losses due to collisions and to channel errors as evaluated by the estimation module.

Abstract: Methods and systems are disclosed for reduced power consumption in communication networks, including sensor networks implemented according to IEEE 802.11ah, by organizing stations into groups having long sleep periods. By organizing the stations of the network into groups, the access point can match each group's traffic identification map with its target beacon transmit time. One embodiment organizes the stations sequentially by AID numbers. Other embodiments organize the stations by similar power save requirements and/or nearby geographical location. Forms of an Extended Traffic Identification Map are matched with an awaken Target Beacon Transmit Time of the group.

Abstract: An electronic component package includes a support and heat conductor. The heat conductor has a protuberance and the support has a socket arranged to be able to receive the protuberance so that the movement of heat conductor relative to the support during the assembly process is reduced.

Abstract: An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer.

Abstract: A power bipolar structure is described having at least one first, one second and one third terminal and including at least one power bipolar transistor having a finger structure coupled to at least one driving block. The power bipolar transistor includes at least one elemental bipolar cell connected to these first, second and third terminals and including at least one power elemental bipolar structure corresponding to a finger of the power bipolar transistor, electrically coupled between the first and second terminals and coupled to a driving section of the driving block by at least one sensing section able to detect information on the operation of the power elemental bipolar structure, the sensing section being in turn coupled to a control circuit and supplying it with a current value as a function of the local temperature of the power elemental bipolar structure.