Abstract: Methods for modifying an Engine Control and Monitoring System (ECaMS) for an engine. A method comprises identifying a provisioning deficit in the ECaMS, wherein the ECaMS comprises a first processor node and a second processor node. The first processor node comprises a first acquisition integrated circuit (IC), a first output IC, and a first processor. The second processor node comprises a second acquisition IC, a second output IC, and a second processor. The first acquisition IC is connected directly to the second acquisition IC. The method comprises connecting an expansion unit to the ECaMS. The expansion unit comprises one or more expansion unit ICs, said one or more expansion unit ICs being connected to one or more ICs of the ECaMS.

Abstract: Engine Control and Monitoring Systems (ECaMS) for engines are disclosed. An ECaMS comprises a first processor node and a second processor node. The first processor node comprises a first acquisition integrated circuit (IC), a first output IC, and a first processor. The second processor node comprises a second acquisition IC, a second output IC, and a second processor. The first acquisition IC is connected directly to the second acquisition IC.

Abstract: Synchronisation methods for synchronising processor nodes of an Engine Control and Monitoring System (ECaMS) for an engine. A method comprises counting, at a first acquisition integrated circuit in a first processor node of the ECaMS, a first control cycle count, and storing at the first acquisition integrated circuit a first transmission slot index. The method further comprises counting a second control cycle count and storing a second transmission slot index at a second acquisition integrated circuit in a second processor node of the ECaMS. The method also comprises transmitting a message including the first control cycle count and transmission slot index from the first to second acquisition integrated circuits, and receiving the message at the second acquisition circuit. The method also comprises synchronising the first and second processor nodes using the first and second control cycle counts and transmission slot indexes.