Abstract: A method of tuning an input/output (I/O) interface of a circuit design for a selected programmable integrated circuit can include determining whether the I/O interface meets a timing requirement and when the I/O interface does not meet the timing requirement, automatically adjusting a first timing setting of the I/O interface of the circuit design. The method can include iteratively determining whether the I/O interface meets the timing requirement, and responsive to each iteration, adjusting the first timing setting. The circuit design, including the adjusted first timing setting, can be output.

Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable circuitry is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath is configured to operate at two frequencies to accommodate the programmable circuitry in the integrated circuit.

Abstract: A media access system in an integrated circuit device having programmable resources for interfacing to a network. The media access system has at least one embedded media access controller configured to provide access to and from the network via a physical layer interface, programmable resources coupled to the embedded controller via a client interface, tie-off pin inputs coupled to the embedded controller for receiving a configuration vector for configuring the embedded controller without having to use a microprocessor for such configuration with the client interface being for communication between the embedded controller and the programmable resources for access to and from the network, and the embedded controller including a multi-mode interface coupled to the client interface for coupling to the programmable resources, the multi-mode interface including a plurality of Media Independent Interface modes, the multi-mode interface configured to be coupled to the physical layer interface.

Abstract: A method and apparatus for improving enforcement of the time-limited operation of a programmable device. Two random number generators, e.g., linear feedback shift register (LFSR) circuits, are utilized in which a first LFSR provides free-running capability, while a second LFSR provides time-sensitive capability. The states of the two LFSR circuits are compared by various portions of the programmable device at each state transition in order to obtain authorization to continue operation. Authorized operation continues as long as the states of both LFSRs are equivalent, or at least equivalent, within a given phase offset. Once a terminal count of the time-sensitive LFSR is reached, then authorization for continued operation ends and at least a portion of the programmable device is disabled.

Abstract: Systems and methods for generating graphic primitives. Data is received that is indicative of a gesture provided by a user. It is determined whether the received gesture data is indicative of a graphic primitive. A graphic primitive is generated for use on a user display based upon said determining step.

Abstract: A media access controller system embedded in an integrated circuit is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in an integrated circuit. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.

Abstract: A transmit-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a transmit engine. A transmit-side datapath is coupled to the media access controller core. The transmit-side datapath is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.

Abstract: A media access controller system embedded in a programmable logic device is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in a programmable logic device. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.

Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath configured is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.

Abstract: A statistics interface for a media access controller is described. The media access controller core includes a receive engine configured to provide a receive statistics vector associated with receive traffic. The receive engine is configured to output the receive statistics vector within an inter-frame gap over a number of receive clock cycles, where a portion of the receive statistics vector is provided with each clock cycle of the receive clock cycles.

Abstract: An aspect of the invention is physical layer interface for a network interface including a plurality of input/output pins. The input/output pins are coupled for being multiplexed into a physical layer interface selected from among a Reduced Gigabit Media Independent Interface and a Gigabit Media Independent Interface. The input/output pins internal to a programmable logic device are for access to and from a processor block located in the programmable logic device.

Abstract: Creating virtual extender plugins using MGTs (Multi-Gigabit Transceivers). A virtual extender plugin allows a user seamlessly to bridge between various FPGAs (Filed Programmable Logic Arrays) when designing and implementing electronic devices. These bridges, provided by these virtual extender plugins, allow for efficient use of various untapped resources within a device. For example, a given FPGA may employ virtual extender plugin(s) to access and use various untapped (or relatively lightly tapped) functionality of other FPGAs. These virtual extender plugins may be implemented according to a relatively wide variety of applications allowing the tapping of unused resources such as memory, microprocessor peripherals, LUTs (Look Up Tables), IOs (Input/Output devices and/or ports), memory, and embedded microprocessor blocks.

Abstract: Systems and methods for generating graphic primitives. Data is received that is indicative of a gesture provided by a user. It is determined whether the received gesture data is indicative of a graphic primitive. A graphic primitive is generated for use on a user display based upon said determining step.