Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: A method of forming adjacent fin field effect transistor devices is provided. The method includes forming at least two vertical fins in a column on a substrate, depositing a gate dielectric layer on the vertical fins, and depositing a work function material layer on the gate dielectric layer. The method further includes depositing a protective liner on the work function material layer, and forming a fill layer on the protective liner. The method further includes removing a portion of the fill layer to form an opening between an adjacent pair of two vertical fins, where the opening exposes a portion of the protective liner. The method further includes depositing an etch-stop layer on the exposed surfaces of the fill layer and protective liner, forming a gauge layer in the opening to a predetermined height, and removing the exposed portion of the etch-stop layer to form an etch-stop segment.

Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: Methods for forming semiconductor fins include forming a protective layer around a base of a hardmask fin on an underlying semiconductor layer. A portion of the hardmask fin is etched away with an etch that is selective to the protective layer. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

Abstract: In accordance with an embodiment of the present invention, a memory cell is provided. The memory cell includes a first L-shaped bottom source/drain including a first dopant, and a first adjoining bottom source/drain region abutting the first L-shaped bottom source/drain, wherein the first adjoining bottom source/drain region includes a second dopant that is the opposite type from the first dopant.

Abstract: A method for modeling planarization performance of a given material includes patterning a first photoresist layer over a first material deposited over a substrate. The method also includes etching portions of the first material exposed by the patterned first photoresist layer to create a patterned topography of the first material comprising two or more different design macros in two or more different regions. The method further includes coating the given material over the patterned topography of the first material, patterning a second photoresist layer over the given material, measuring the critical dimension of a metrology feature in each of the two or more different regions, and utilizing the measured critical dimensions of the metrology feature in the two or more different regions to generate a model of the planarization performance of the given material by relating the measured critical dimensions to focal planes of the given material.

Abstract: Embodiments of the invention are directed to configurations of semiconductor devices. A non-limiting example configuration includes a plurality of first transistors formed over a performance region of a major surface of a substrate. Each of the plurality of first transistors includes a first channel fin structure and a first gate structure along at least a portion of a sidewall surface of the first channel fin structure. The first gate structure includes a first gate thickness dimension. A plurality of second transistors is formed over a density region of the major surface of the substrate. Each of the plurality of second transistors includes a second channel fin structure and a second gate structure along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

Abstract: Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure is formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

Abstract: A method of forming adjacent fin field effect transistor devices is provided. The method includes forming at least two vertical fins in a column on a substrate, depositing a gate dielectric layer on the vertical fins, and depositing a work function material layer on the gate dielectric layer. The method further includes depositing a protective liner on the work function material layer, and forming a fill layer on the protective liner. The method further includes removing a portion of the fill layer to form an opening between an adjacent pair of two vertical fins, where the opening exposes a portion of the protective liner. The method further includes depositing an etch-stop layer on the exposed surfaces of the fill layer and protective liner, forming a gauge layer in the opening to a predetermined height, and removing the exposed portion of the etch-stop layer to form an etch-stop segment.

Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.

Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

Abstract: A semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.

Abstract: A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.

Abstract: Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.

Abstract: Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.