Abstract: A tiered memory system includes a tiered memory management system that is coupled to a first memory subsystem associated with a first memory subsystem tier, and a second memory subsystem associated with a second memory subsystem tier that is different than the first memory subsystem tier. The tiered memory management system monitors a health of the first memory subsystem associated with the first memory subsystem tier and the second memory subsystem associated with the second memory subsystem tier. When the tiered memory management system identifies a health issue with the first memory subsystem associated with the first memory subsystem tier, it moves data stored in the first memory subsystem associated with the first memory subsystem tier to the second memory subsystem associated with the second memory subsystem tier.

Abstract: A shared memory fabric workload performance system includes a resource orchestrator device coupled to processing systems and memory systems that are configured to provide a shared memory fabric to each of the processing systems. The resource orchestrator device receives a request to perform a workload, identifies functions for performing the workload, and generates a DAG that identifies a respective processing resource type and a respective memory requirement for performing each of the functions. For each of the functions, the resource orchestrator device determines a respective processing resource provided by the processing systems that includes the processing resource type identified in the DAG for performing that function, and a respective memory resource provided by the memory systems that is accessible to that respective processing resource, and maps that respective memory resource to that respective processing resource based on the memory requirement identified in the DAG for performing that function.

Abstract: A resource-capability-and-connectivity-based workload performance improvement system includes a resource management device coupled to processing systems and memory systems. The resource management device receives a request to perform a first workload, identifies a DAG that includes functions for performing the first workload, and uses first parameters in the DAG to configure the processing systems and the memory subsystems to perform the functions. Based on performance of the functions, the resource management device determines function modification(s) for at least one of the functions and, based on the function modification(s), modifies the first parameters included in the DAG to provide modified parameters. When the resource management device receives a request to perform a second workload, it identifies the DAG that includes the functions for performing the second workload, and uses the modified parameters in the DAG to configure the processing systems and the memory subsystems to perform the functions.

Abstract: A resource-capability-and-connectivity-based workload performance system includes a resource management system that is coupled to a plurality of processing systems and a plurality of memory systems. The resource management system determines resource capabilities provided by each of the plurality of processing systems, each of the plurality of memory systems, and connectivity between the plurality of processing systems and the plurality of memory systems.

Abstract: An information handling system includes a first memory device that provides a first system physical address (SPA) space for the information handling system having a first capacity. Data is stored on the first memory device with a first interleave configuration. A second memory device provides a second SPA space for the information handling system that has a second capacity that is greater than or equal to the first capacity. Without rebooting the information handling system and without halting a process, the system de-interleaves the data stored on the first memory device, stores the data on the second memory device, and re-interleaves the data.

Abstract: A tiered memory system includes a tiered memory management system that is coupled to a first memory subsystem associated with a first memory subsystem tier, and a second memory subsystem associated with a second memory subsystem tier that is different than the first memory subsystem tier. The tiered memory management system monitors a health of the first memory subsystem associated with the first memory subsystem tier and the second memory subsystem associated with the second memory subsystem tier. When the tiered memory management system identifies a health issue with the first memory subsystem associated with the first memory subsystem tier, it moves data stored in the first memory subsystem associated with the first memory subsystem tier to the second memory subsystem associated with the second memory subsystem tier.

Abstract: An information handling system includes a first memory device that provides a first system physical address (SPA) space for the information handling system having a first capacity. Data is stored on the first memory device with a first interleave configuration. A second memory device provides a second SPA space for the information handling system that has a second capacity that is greater than or equal to the first capacity. Without rebooting the information handling system and without halting a process, the system de-interleaves the data stored on the first memory device, stores the data on the second memory device, and re-interleaves the data.

Abstract: An information handling system includes a processor and a Compute express link (CXL) device. The CXL device is coupled to the processor by a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a first data rate, trains the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and operates the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate.

Abstract: Disclosed is the compound vitamin D3 phosphate and pharmaceutically acceptable salts thereof, pharmaceutical compositions comprising the compound and methods for preparing the compound. Also disclosed are methods of treating vitamin D deficiency using the compound. The compound is particularly suitable for transdermal delivery.

Abstract: An information handling system includes a compute express link (CXL) device coupled to a processor by a PCIe/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a CXL link signaling rate, trains the PCIe/CXL link as a PCIe link in response to determining that the PCIe/CXL link failed to train to the CXL link signaling rate, and operates the CXL device as a PCIe device only in response to training the PCIe/CXL link as a PCIe link.

Abstract: An information handling system includes a memory controller coupled to a first memory device and to a second memory device. The first and second memory devices are configured to receive memory access requests addressed based upon a device physical address (DPA) space of the memory controller. The memory controller incudes a page redirection table having an entry for each page of a host physical address (HPA) space of the information handling system corresponding with the pages of the DPA space. Each entry of the page redirection table associates the particular page of the HPA space with a page within the DPA space. The memory controller receives memory access requests addressed with HPAs from a host processor, and fulfills the memory access requests from a selected one of the first and second memory devices based upon DPAs determined from the entries of the page redirection table.

Abstract: An information handling system includes a first memory device that provides a first system physical address (SPA) space for the information handling system having a first capacity. Data is stored on the first memory device with a first interleave configuration. A second memory device provides a second SPA space for the information handling system that has a second capacity that is greater than or equal to the first capacity. Without rebooting the information handling system and without halting a process, the system de-interleaves the data stored on the first memory device, stores the data on the second memory device, and re-interleaves the data.

Abstract: An information handling system utilizes data with a cache line size. A memory module is coupled to a memory controller by a memory bus, and stores and retrieves data with a memory line size. The cache line size is an integer multiple of the memory line size. The memory controller calculates error correction code data for each memory line of user data, and generates metadata related to the user data for chunks of data that are equal to an integer number (N) of cache lines, where N is greater than one.

Abstract: An information handling system includes a compute express link (CXL) multi-port controller (MPC). A first processor includes first memory modules coupled to the first processor. A second processor includes second memory modules coupled to the second processor. The CXL MPC is coupled via a first CXL port to the first processor and is coupled via a second CXL port to the second processor. The CXL MPC includes third memory modules coupled to the CXL MPC. The first memory modules, the second memory modules, and the third memory modules comprise a common cache coherency domain.

Abstract: An information handling system utilizes data with a cache line size. A memory module is coupled to a memory controller by a memory bus, and stores and retrieves data with a memory line size. The cache line size is an integer multiple of the memory line size. The memory controller calculates error correction code data for each memory line of user data, and generates metadata related to the user data for chunks of data that are equal to an integer number (N) of cache lines, where N is greater than one.

Abstract: An information handling system includes a processor and a Compute express link (CXL) device. The CXL device is coupled to the processor by a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a first data rate, trains the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and operates the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate.

Abstract: An information handling system includes a processor having a first data storage device in a first memory tier, a second data storage device in a second memory tier, and a tiering manager. The first tier exhibits first data storage attributes and the second tier exhibits second data storage attributes. The tiering manager receives first memory access information from the first data storage device and second memory access information from the second data storage device, makes a determination that a first performance level of the information handling system when first data is stored in the first data storage device can be improved to a second performance level of the information handling system by swapping the first data to the second data storage device based upon the first memory access information and the second memory access information, and swaps the first data to the second data storage device in response to the determination.

Abstract: An information handling system includes a compute express link (CXL) device coupled to a processor by a PCIe/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a CXL link signaling rate, trains the PCIe/CXL link as a PCIe link in response to determining that the PCIe/CXL link failed to train to the CXL link signaling rate, and operates the CXL device as a PCIe device only in response to training the PCIe/CXL link as a PCIe link.

Abstract: An information handling system includes first and second memory modules, and a central processing unit. The first memory module includes one or more memory ranks of memory devices, and a first plurality of thermal sensors. The second memory module includes one or more memory ranks of memory devices, and a second plurality of thermal sensors. The central processing unit receives first thermal telemetry data for the first memory module from the first thermal sensors, and second thermal telemetry data for the second memory module from the second thermal sensors. In response to the reception of the first thermal telemetry data, the central processing unit determines a first localized temperature of a first memory rank. In response to the first localized temperature exceeding a threshold temperature, the central processing unit re-maps access of data from the first memory rank to a second memory rank.

Abstract: An information handling system includes a memory module having a first thermal sensor for a first memory channel, and a second thermal sensor for a second memory channel. A processor receives a first temperature from the first thermal sensor and a second temperature from the second thermal sensor, and performs a first high bandwidth access of the first memory channel. In response to a predetermined amount of time ending, the processor: receives a third temperature from the first thermal sensor and a fourth temperature from the second thermal sensor; determines a first temperature delta based on a difference between the third and first temperatures; and determines a second temperature delta based on a difference between the fourth and second temperatures. Based on the first and second temperature deltas, the processor determines whether the first or second memory channel is an upstream memory channel.