Patents by Inventor Stuart B. Shacter
Stuart B. Shacter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7233171Abstract: A transconductance stage is provided. The transconductance stage includes a tail current source, a differential pair, and two current mirrors. The input to each of the current mirrors is connected to the drain of a separate one of the transistors in the differential pair. The two current mirrors each have two outputs so that one of the outputs can be used to determine whether the output current exceeds a threshold (e.g. nine-tenths of the tail current). If the source current exceeds the threshold, extra source current is switched in to the output so that output source current is increased. Similarly, if the sink current exceeds the threshold, extra sink current is switched in to the output so that the output sink current is increased. This way, the transconductance stage can supply large output currents in response to a large signal input but maintains low quiescent current for small input signals.Type: GrantFiled: June 29, 2005Date of Patent: June 19, 2007Assignee: National Semiconductor CorporationInventors: Stuart B. Shacter, Yinming Chen
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Patent number: 6710660Abstract: A circuit is arranged as a class B amplifier with a rail-to-rail output swing and a small deadband. The circuit has two parallel input stages that each use an amplifier configured as a unity gain voltage follower. The output of each stage drives a high current output transistor. The output transistors are complementary transistors arranged in a common source configuration. The common source configuration operates as a complementary class B amplifier, which conducts no quiescent bias current. An offset voltage is introduced in each input stage, which creates a small deadband in the output voltage as it switches between sinking current and sourcing current. The offset voltage is selected to ensure that the output transistors are not both simultaneously activated.Type: GrantFiled: September 17, 2002Date of Patent: March 23, 2004Assignee: National Semiconductor CorporationInventor: Stuart B. Shacter
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Patent number: 6657420Abstract: A method and apparatus provide for accurate low current generation using switched capacitor techniques. The current generator includes a reference voltage generator that provides a reference signal to a switched capacitor integrator. In one example, the reference circuit includes a switched capacitor divider. The switched capacitor integrator circuit produces a voltage ramp in response to the reference signal and other timing signals. The rate of the voltage ramp is proportional to the ratio of capacitors in the switched capacitor integrator and a clock frequency that is associated with the timing signals. A feedback circuit impresses the voltage ramp across an output capacitor circuit that has a very low capacitance value. The capacitor is arranged to differentiate the voltage ramp to produce an accurate low current. The switched capacitor design is suitable for integration in a monolithic integrated circuit. The integrator and the feedback stage are periodically reset.Type: GrantFiled: October 19, 2001Date of Patent: December 2, 2003Assignee: National Semiconductor CorporationInventor: Stuart B. Shacter
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Patent number: 6316978Abstract: A comparator circuit having a first state and a second state, a threshold potential for transition from the first state to the second state, another threshold potential for transition from the second state to the first state, and hysteresis characteristics that are independent of process, temperature, and supply voltage variations. Preferably, the threshold potentials and hysteresis characteristics depend only on a reference potential and on ratios of resistances of pairs of resistors.Type: GrantFiled: May 3, 2000Date of Patent: November 13, 2001Assignee: National Semiconductor CorporationInventor: Stuart B. Shacter
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Patent number: 6316995Abstract: An amplifier input stage having a constant input gm and including first and second differential transistor pair so as to provide operation with inputs at or near the upper and lower power supply rails. A comparator circuit operates to control which of the transistor pair is active based upon the relative magnitudes of the amplifier input stage inputs and a reference voltage.Type: GrantFiled: June 2, 2000Date of Patent: November 13, 2001Assignee: National Semiconductor CorporationInventors: Sean S. Chen, Stuart B. Shacter
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Patent number: 6225782Abstract: A circuit for providing hi-Z charging of a deeply discharged battery includes a load simulator circuit to provide a charging load resistance even when the battery has been discharged to 0V. The load simulator circuit includes a transistor connected in series with the battery. A logic circuit detects when the battery voltage is below a minimum threshold voltage and instructs a voltage control circuit to provide a constant voltage across the battery and the load simulator circuit. The logic circuit also applies the output of a current control circuit to the gate terminal of the transistor, enabling the current control circuit to regulate the total resistive load of the battery-transistor pair and thus maintain a constant hi-Z charge current across the battery.Type: GrantFiled: November 4, 1998Date of Patent: May 1, 2001Assignee: National Semiconductor CorporationInventors: Mark J. Mercer, Stuart B. Shacter
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Patent number: 6166521Abstract: A control circuit is provided to minimize the charging cycle time of a battery charging system by maximizing the length of time that high constant charging current is applied to a discharged battery. The control circuit includes a constant current (CC) error amplifier, a constant voltage (CV) error amplifier, an output amplifier, and two pole-splitting compensation networks. The control circuit works in conjunction with a power source to charge a secondary battery. The pole-splitting compensation networks allow the CC, CV, and output amplifiers to be configured for high gain, without sacrificing output stability. The control circuit provides a sharp transition between the CC mode and CV mode of operation. In the CC mode, fast bulk battery charging is provided. In the CV mode, the control circuit initially provides a "top-off" charge to the battery and subsequently safely maintains the battery at its fully charged state.Type: GrantFiled: April 17, 2000Date of Patent: December 26, 2000Assignee: National Semiconductor CorporationInventors: Mark J. Mercer, Stuart B. Shacter
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Patent number: 6100667Abstract: A control circuit is provided to minimize the charging cycle time of a battery charging system by maximizing the length of time that high constant charging current is applied to a discharged battery. The control circuit includes a constant current (CC) error amplifier, a constant voltage (CV) error amplifier, an output amplifier, and two pole-splitting compensation networks. The control circuit works in conjunction with a power source to charge a secondary battery. The pole-splitting compensation networks allow the CC, CV, and output amplifiers to be configured for high gain, without sacrificing output stability. The control circuit provides a sharp transition between the CC mode and CV mode of operation. In the CC mode, fast bulk battery charging is provided. In the CV mode, the control circuit initially provides a "top-off" charge to the battery and subsequently safely maintains the battery at its fully charged state.Type: GrantFiled: January 21, 1999Date of Patent: August 8, 2000Assignee: National Semiconductor CorporationInventors: Mark J. Mercer, Stuart B. Shacter
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Patent number: 5570067Abstract: An RC oscillator operates at very low current levels and manifests very brief internal component delays. The RC oscillator does not employ a conventional comparator and a conventional hysteresis circuit for changing reference voltages on the comparator. Instead, the RC oscillator includes a plurality of amplifiers. Hysteresis is achieved by changing the threshold voltage of one of the amplifiers. The threshold voltage is changed by switching different current values through the transistor so that the current for activating the amplifier is different from the current for deactivating the amplifier.Type: GrantFiled: June 6, 1995Date of Patent: October 29, 1996Assignee: National Semiconductor CorporationInventor: Stuart B. Shacter
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Patent number: 5442320Abstract: A complementary transistor class AB output stage (200) utilizes a complementary pair of output drivers (220, 222) connected in series between the power supply rails (210, 216) to furnish the stage output. An output driver (206) is a composite pair of transistors in a Darlington configuration, which boosts the current gain and input resistance of the output stage. Bases of the output drivers are connected by a complementary pair of parallel connected drivers (226, 228), which function as common base level shifters. Quiescent bias of the output drivers is achieved by a pair of constant current transistors (232, 238) that are operated as complementary current mirrors. Inputs to the mirrors are relatively low current sink (252) and source (250) supplies.Type: GrantFiled: June 9, 1994Date of Patent: August 15, 1995Assignee: National Semiconductor CorporationInventors: David J. Kunst, Stuart B. Shacter
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Patent number: 4968901Abstract: An attenuator for use in an integrated circuit window comparator circuit provides voltage division across an input voltage divider including a large number of identical thin film resistor segments combined in various series and parallel arrangements so that resistive voltage division of the input signal is in the same ratio as capacitive voltage division of the input signal by parasitic capacitances of the resistors.Type: GrantFiled: May 16, 1989Date of Patent: November 6, 1990Assignee: Burr-Brown CorporationInventor: Stuart B. Shacter
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Patent number: 4409561Abstract: In an operational amplifier, the output of the differential first stage is applied directly to the base electrode of a voltage gain transistor which in turn drives the remainder of the operational amplifier output stage. A pair of junction field-effect-transistors in conjunction with a diode and a current mirror circuit are employed to set the quiescent voltage at the circuit output. Both pull-up and pull-down transistors are employed to achieve the correct output in response to an input at the base of the voltage gain transistor.Type: GrantFiled: April 13, 1981Date of Patent: October 11, 1983Assignee: Motorali, Inc.Inventor: Stuart B. Shacter
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Patent number: 4393355Abstract: The gain and phase characteristics of an operational amplifier are improved by adding a system zero to cancel a pole and thereby broadband the amplifier. This is accomplished by simultaneously driving the base terminals of the second stage gain transistor and preceding follower transistor and biasing the circuit such that the dynamic emitter resistance of the follower transistor is much greater than that of the gain transistor and/or by adding an additional emitter impedance.Type: GrantFiled: October 26, 1981Date of Patent: July 12, 1983Assignee: Motorola, Inc.Inventors: William F. Davis, Stuart B. Shacter
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Patent number: 4390850Abstract: An operational amplifier includes in its first stage current splitting means which enables the slew rate to be varied independently of bandwidth. A pair of dual collector transistors are coupled between the amplifier's input devices and a current mirror circuit. Only one collector of each of the split collector devices is coupled to the current mirror circuit and the current flowing therethrough is controlled by varying the area of the second collector. Slew rate and bandwidth are then controlled by proper selection of current and the ratio of the collector areas.Type: GrantFiled: March 16, 1981Date of Patent: June 28, 1983Assignee: Motorola, Inc.Inventors: William F. Davis, Stuart B. Shacter
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Patent number: 4387309Abstract: An input stage for an operational amplifier comprises junction field-effect-transistor input devices having common sources and having their drain electrodes coupled to a PNP level shifting arrangement which in turn drives an NPN current mirror circuit. The level shifting arrangement comprises first and second PNP transistors coupled in a common base configuration with their emitters coupled to the drains of the input JFETS. The level shifting transistor are biased on so as always conduct current to the current mirror circuit.Type: GrantFiled: July 6, 1981Date of Patent: June 7, 1983Assignee: Motorola, Inc.Inventor: Stuart B. Shacter