Abstract: One aspect of the application can provide a system and method for replacing a failing node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node-migration condition is met, the system can initialize a node controller of the spare node such that accesses to a memory local to the spare node are to be processed by the node controller, quiesce the failing node and the spare node to allow state information of processors on the failing node to be migrated to processors on the spare node, and subsequent to unquiescing the failing node and the spare node, migrate data from the failing node to the spare node while maintaining cache coherence in the NUMA system and while the NUMA system remains in operation, thereby facilitating continuous execution of processes previously executed on the failing node.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: A heat spreader with multiple stacked printed circuit boards (PCBS) includes top and side sections within which a first PCB is contained and bottom edges that extend to a second PCB. The heat spreader and second PCB substantially enclose the first PCB therein.

Abstract: Embodiments include apparatus, methods, and systems having a multi-chip module with a power system and pass-thru holes. An exemplary electronic module includes a first portion having a first printed circuit board (PCB) with a memory and plural processors. A second portion has a power system and a thermal dissipation device. The thermal dissipation device has plural extensions, and the power system has plural pass-thru holes. The first portion electrically couples to the second portion to form the electronic module when the plural extensions extend through the plural pass-thru holes of the power system and through plural pass-thru holes of a second PCB disposed between the first and second portions.

Abstract: In one embodiment, a distributed redundant control signal distribution system comprises a first control signal source co-located with a first set of control signal controlled circuit elements, at least one second control signal source co-located with a second set of control signal controlled circuit elements, at least one controller for providing control signals from the first control signal source to control both the first and second sets of controlled circuit elements, the controller operable for substituting signals from the second control signal source for signals from the first signal control source if the signals from the first control signal source become unavailable to either the first or second circuit elements.

Abstract: Embodiments include apparatus, methods, and systems of an electronic module for a system board having at least one pass-thru hole. An exemplary electronic module, connectable to a system board with a pass-thru hole, includes a first portion coupled to one side of the system board. The first portion has a printed circuit board (PCB) with plural processors. A second portion of the electronic module couples to a second, opposite side of the system board. The second portion has a power system board electrically coupled to the first portion. The second portion also includes a thermal dissipation device that extends through the pass-thru hole of the system board.

Abstract: A test method characterizes current behavior of power components (e.g., semiconductor packages) within an electronic system. One or more electrically conductive loops are formed with a first printed circuit board of the electronic system; these loops surround, at least in part, one or more electrical vias of the first printed circuit board. One or more power components connect to the vias to obtain power therethrough. Current characteristics are measured from one or more vias to assess transient and steady-state currents of components within the system. Power dissipation may be determined from the current. The loops may be formed within tracks of internal layers of the first printed circuit board, or a second printed circuit board may form the tracks.

Abstract: A circuit comprising multiple circuit boards is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.

Abstract: An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.

Abstract: A stacked electronic device module is constructed incorporating heat pipes within the module, enabling efficient cooling of the electronic devices within the module. The heat pipes may extend outside of the stacked electronic device modules for more efficient operation. Heat pipes may be placed selectively between some layers of the module or placed between each layer of the module.

Abstract: A test method characterizes current behavior of power components (e.g., semiconductor packages) within an electronic system. One or more electrically conductive loops are formed with a first printed circuit board of the electronic system; these loops surround, at least in part, one or more electrical vias of the first printed circuit board. One or more power components connect to the vias to obtain power therethrough. Current characteristics are measured from one or more vias to assess transient and steady-state currents of components within the system. Power dissipation may be determined from the current. The loops may be formed within tracks of internal layers of the first printed circuit board, or a second printed circuit board may form the tracks.

Abstract: A circuit comprising is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.

Abstract: A high performance processor assembly is electrically connected to a power supply so as to minimize voltage variations associated with the supply of power to the processor assembly. The processor assembly is fabricated on a multilayered printed circuit board. Power is supplied to components on the printed circuit board by way of parallel and split power planes. The parallel and split power planes reduce inductance and increase capacitance associated therewith. The reduced inductance reduces voltage variations caused by load transient currents. Capacitors are electrically connected to the power planes by way of multiple vias to further reduce inductance.