Abstract: A circuit for generating signals in a data processing system has a passive delay line and logic gates connected to the output taps of the delay line. Isolation resistors are connected between the output taps and the logic gates in order to substantially reduce signal reflections in the signal path within the delay line that are caused by the input capacitance of the logic gates.

Abstract: A computer system clock generator generates several system clock signals which are in a tuned state at desired locations, thereby offsetting the effects of varying propagation delays among the system clock signals. A shift register ring has one of its taps selectively connected to its data input so that a series of logic high level and logic low level data is advanced through the shifting stages. A tap selector for each desired output signal logically combines the signals output from the appropriate taps to produce output clock signals having desired leading and trailing edges.

Abstract: A clock distribution system having a generator for generating a train of pulses, a transition circuit connected to the output of the generator for generating a clock signal having spaced apart transitions of a desired polarity, a distribution circuit distributing the clock signal to a plurality of boards which utilize the clock signal, and a flip-flop on each of the boards which utilize the clock signal. Each of the flip-flops is connected to the distribution circuit for receiving the clock signal and for generating clock pulses which are defined by the spaced apart transitions.