Patents by Inventor Stuart D Biles

Stuart D Biles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8725953
    Abstract: A data processing system including a plurality of processors 4, 6, 8 each having a local cache memory 10, 12, 14 is provided. A cache coherency controller 16 serves to maintain cache coherency between the local cache memories 10, 12, 14. When one of the processors 4, 6, 8 is placed into a low power state its associated local cache memory 10, 12, 14 is maintained in a state in which the data it is holding is accessible to the cache coherency controller 16 until a predetermined condition has been met whereupon the local cache memory 10, 12, 14 concerned is placed into a low power state. The predetermined condition can take a variety of different forms such as the rate of snoop hits falling below a threshold value, the ratio of snooping hits to snoop requests falling below a threshold value, a predetermined number of clock cycles passing since the associated processor for that local cache memory was powered down as well as other possibilities.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: May 13, 2014
    Assignee: ARM Limited
    Inventors: Nigel C Paver, Stuart D Biles, Kevin P Welton, Paul G Meyer
  • Publication number: 20100185821
    Abstract: A data processing system including a plurality of processors 4, 6, 8 each having a local cache memory 10, 12, 14 is provided. A cache coherency controller 16 serves to maintain cache coherency between the local cache memories 10, 12, 14. When one of the processors 4, 6, 8 is placed into a low power state its associated local cache memory 10, 12, 14 is maintained in a state in which the data it is holding is accessible to the cache coherency controller 16 until a predetermined condition has been met whereupon the local cache memory 10, 12, 14 concerned is placed into a low power state. The predetermined condition can take a variety of different forms such as the rate of snoop hits falling below a threshold value, the ratio of snooping hits to snoop requests falling below a threshold value, a predetermined number of clock cycles passing since the associated processor for that local cache memory was powered down as well as other possibilities.
    Type: Application
    Filed: January 21, 2009
    Publication date: July 22, 2010
    Applicant: ARM LIMITED
    Inventors: Nigel C. Paver, Stuart D. Biles, Kevin P. Welton, Paul G. Meyer
  • Patent number: 7350055
    Abstract: An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: March 25, 2008
    Assignee: Arm Limited
    Inventors: Stuart D. Biles, Krisztian Flautner, Scott Mahlke, Nathan Clark
  • Patent number: 7318143
    Abstract: An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store operable to store operand values and an accelerator having a plurality of functional units. The accelerator executes a combined operation corresponding to a computational sub-graph of the separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with the combined operation. The accelerator executes the combined operation in dependence upon operand mapping data providing a mapping between operands of the combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between the plurality of functional units and the particular processing operations.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: January 8, 2008
    Assignees: ARM Limited, University of Michigan
    Inventors: Stuart D. Biles, Krisztian Flautner, Scott Mahlke, Nathan Clark
  • Patent number: 7111126
    Abstract: An apparatus and method for loading data values from a memory system are provided. The data processing apparatus comprises a data processing unit operable to execute instructions, and a register file having a plurality of registers operable to store data values accessible by the data processing unit when executing the instructions. Further, a holding register is provided which does not form one of a working set of registers of the register file, and is operable to temporarily store a data value, the holding register having a data portion for storing the data value, and an identifier portion operable to store identifier data associated with the data value.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: September 19, 2006
    Assignee: ARM Limited
    Inventors: Stuart D Biles, Christopher B Dornan, Vladimir Vasekin, Andrew C Rose