Abstract: In accordance with one embodiment of the present invention, a semiconductor device underbump metallurgy (414) is formed over a semiconductor bond pad (128), wherein the underbump metallurgy (414) comprises a chromium, copper, and nickel phased-region (404), and wherein the presence of nickel in the phased-region (404) inhibits conversion of tin from the solder bump and other tin sources from forming spallable Cu6Sn5 copper-tin intermetallics.

Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Abstract: In accordance with one embodiment of the present invention, a semiconductor device underbump metallurgy (414) is formed over a semiconductor bond pad (128), wherein the underbump metallurgy (414) comprises a chromium, copper, and nickel phased-region (404), and wherein the presence of nickel in the phased-region (404) inhibits conversion of tin from the solder bump and other tin sources from forming spallable Cu6Sn5 copper-tin intermetallics.

Abstract: In accordance with one embodiment of the present invention, a semiconductor device underbump metallurgy (414) is formed over a semiconductor bond pad (128), wherein the underbump metallurgy (414) comprises a chromium, copper, and nickel phased-region (404), and wherein the presence of nickel in the phased-region (404) inhibits conversion of tin from the solder bump and other tin sources from forming spallable Cu6Sn5 copper-tin intermetallics.

Abstract: A mostly copper-containing interconnect (126) overlies a semiconductor device substrate (100), and a transitional metallurgy structure (312, 508, 716, 806) that includes an aluminum-containing film (200, 506, 702, 802) contacts a portion of the mostly copper-containing interconnect. In one embodiment, the transitional metallurgy is formed over a portion of a bond pad (128). In an alternative embodiment, the transitional metallurgy includes an energy alterable fuse portion (710) that electrically contacts two conductive regions (712 and 714), and in yet another embodiment, the transitional metallurgy is formed over a copper-containing edge seal portion (809).

Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Abstract: Conductive bumps (32) are formed to overlie a semiconductor die (11). The conductive bumps (32) typically have reduced levels of lead, flow at a temperature no greater than 260° C., and have reduced problems associated with alpha particles. In one embodiment, the conductive bump (32) includes a mostly tin (20) with a relatively thin layer of lead (30). The lead (30) and a portion of the tin (20) interact to form a relatively low melting solder close to the eutectic point for lead and tin. Most of the tin (20) remains unreacted and can form a stand off between the semiconductor die (11) and the packaging substrate (42). Other metals and impurities can be used to improve the mechanical or electrical properties of the conductive bumps (32).

Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Abstract: Multiplexed joining of solder bumps to various substrates for assembly of an integrated circuit package includes placing a semiconductor substrate (312) having solder bump structures (314) in contact with a ceramic substrate (320 having chip pads (322, 334), and placing this structure in contact with ball grid array spheres (352) in order to form a CBGA (360) in a single flow process.

Abstract: A method of forming an interconnect bump structure (32, 33). Under Bumb Metalization 11 (UBM) comprising a chrome layer (16), a copper layer (36), and a tin layer (40) is disclosed. In one embodiment, eutectic solder (45) is then formed over the UBM (11) and reflowed in order to form the interconnect bump stucture. In another embodement, a lead standoff (46) is formed over the UBM (11) before the formation of the eutectic solder (48).

Abstract: Flip-chip is fast becoming the mounting method of choice in the semiconductor industry for dice having a high number of contacts. Since many applications require known-good-die, these flip-chip semiconductor dice must be tested and burned-in. By testing and burning-in the semiconductor wafers prior to solder bumping, the probe tips (42, 44, 46 & 48) can contact the hard planar surface of the under-bump-metallurgy (40) on each bonding pad (14) for easier and more reliable contact and hence test results. The probe tips can be either of an array (42 & 44) or cantilevered needle (46 & 48) type. Blunt probe tips (42 & 48) are well-suited to making contact on the shoulder of each bonding pad of each semiconductor die, while sharp probe tips (44 & 46) are preferable for contacting the center of each bonding pad. Solder bumping is performed post-testing.

Abstract: A semiconductor device (32) has an as-deposited solder bump (34) having the intrinsic potential for forming an extended eutectic region for simplified DCA applications. The as-deposited solder bump (34) has first tin layer (40) overlying the UBM of the bonding pad (14) on the device. The first tin layer reacts with a metal layer (36) in the UBM to form an intermetallic for adhering the solder bump to the bonding pad. A thick lead layer (42) overlies the first tin layer to provide the substantial component of the solder bump. A second tin layer (44) overlies the lead layer to provide localized eutectic formation at the top surface of the bump during reflow. A device having at least this solder bump structure can be directly attached to either ceramic or PC board substrates. Additional layers of tin and /or lead may be supplemented to the basic bump structure to optimize the eutectic formation rate.

Abstract: A nodular metal paste (42) is used to temporarily attach the bumps (34) on a semiconductor die (32) to a substrate (38). The spherical nodules (44) composing the metal paste are dispensed onto contact pads (40) on the substrate, and then heated until they partially melt. The partial liquid region permits bonding of the individual metal nodules to the contact pads and to adjacent nodules. Subsequently, a bumped die is placed over the nodules and heated to a minimum temperature required to partially remelt to form a local tack joint. Because the metallurgical contact area between the paste nodules and the bumps is minimized, electrical contact can be sustained with a small cross-sectional area of connected material to create an electrically sound but physically weak link between die and the substrate. Once connected to the substrate, the die may be tested and burned-in, and removed afterwards with little damage to the bumps.

Abstract: A method and apparatus for depositing the material onto a substrate is provided. The apparatus includes a mesh member which has impregnated therein the material which is to be vapor deposited. The mesh member with the material thereon is heated to vaporize the material and the vaporized material is then deposited onto the desired substrate. Preferably the material that is deposited is maintained in a crucible having an opening and the mesh member is disposed over the opening. The material in the crucible is vaporized and condensed onto the mesh member, and the condensed material wicks through the mesh member and then revaporizes from the top of the mesh member and is deposited onto the substrates.

Abstract: A process is described for selective removal of unwanted metallization from the surface of a semiconductor device. The process comprises the usual deposition of a configurable image defining layer on the surface of the device upon which a suitable pad limiting metallurgy (PLM) has already been deposited. The layer is then opened over the pad limiting metallurgy using standard techniques and coated with a layer of the terminal metal. The coated device is then heated to just above the melting point of the terminal metal causing the melted metal, through surface tension to form a ball of metal on the PLM and to form small globules of metal on the surface of the layer and then permitted to cool. When cooled the layer is removed using the usual techniques. Because the coating of terminal metal is no longer a continuous layer on the surface of the mask, removal of the polymer mask can be accomplished in about one-tenth of the time required when compared to a deposited terminal metal layer that is not melted.

Abstract: A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset substrate conductors.

Abstract: A method of making an aperture of a predetermined shape into a dielectric substrate which will lockingly receive a deformable contact pin. It includes providing a dielectric material which shrinks in response to a heat treatment by an amount which is different in one direction from that in another direction, and which irreversibly changes dimensions in its two orthogonal directions in proportion to this difference. An aperture is formed in such a material, in a direction normal to the plane of the two orthogonal directions and the material is subjected to a heat treatment that causes a differential shrinkage in the aperture and a change in the shape of the aperture. A deformable contact pin is then forced into a locking position in the aperture.

Abstract: The coating of a conductor pattern on dielectric green sheets to a common edge thereof with stacking or superimpositioning together of a plurality of sheets to enclose the conductor pattern followed by sintering, with the edge side of the fired body having the exposed end terminations becoming the actual face of the body on which a semiconductor device is mounted in electrical circuit connection to respective ones of the common end terminations of the conductor runs. The conductor runs are returned through the body to the active face of the body to position the opposite or distal ends of the conductors thereat, in an increased spaced relationship of the distal conductor terminations. For external connection, terminal pins may be embedded in the fired body for connection at adjacent and to the distal conductor termination, with the pins projecting therefrom.