Abstract: A single-instruction/multiple-data (SIMD) processor uses a function unit that can perform a single operation on multiple data elements. The function unit operates at a higher speed than the rest of the processor, allowing each data element in the SIMD operand to be processed sequentially, using fewer compute resources and avoiding any processing throughput loss. The SIMD processor includes an input register that receives N data elements at the beginning of a clock cycle in a slow clock domain. Each data element of the operand is selected and passed to the function unit on consecutive clock cycles in a fast clock domain. The N results are generated on N successive clock cycles in the fast clock domain and combined to provide multiple results on a single clock cycle in the slow clock domain.